/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2018 Oleksij Rempel <[email protected]> * * Driver for Alcor Micro AU6601 and AU6621 controllers */ #ifndef __ALCOR_PCI_H #define __ALCOR_PCI_H #define ALCOR_SD_CARD … #define ALCOR_MS_CARD … #define DRV_NAME_ALCOR_PCI_SDMMC … #define DRV_NAME_ALCOR_PCI_MS … #define PCI_ID_ALCOR_MICRO … #define PCI_ID_AU6601 … #define PCI_ID_AU6621 … #define PCI_ID_AU6625 … #define MHZ_TO_HZ(freq) … #define AU6601_BASE_CLOCK … #define AU6601_MIN_CLOCK … #define AU6601_MAX_CLOCK … #define AU6601_MAX_DMA_SEGMENTS … #define AU6601_MAX_PIO_SEGMENTS … #define AU6601_MAX_DMA_BLOCK_SIZE … #define AU6601_MAX_PIO_BLOCK_SIZE … #define AU6601_MAX_DMA_BLOCKS … #define AU6601_DMA_LOCAL_SEGMENTS … /* registers spotter by reverse engineering but still * with unknown functionality: * 0x10 - ADMA phy address. AU6621 only? * 0x51 - LED ctrl? * 0x52 - unknown * 0x61 - LED related? Always toggled BIT0 * 0x63 - Same as 0x61? * 0x77 - unknown */ /* SDMA phy address. Higher then 0x0800.0000? * The au6601 and au6621 have different DMA engines with different issues. One * For example au6621 engine is triggered by addr change. No other interaction * is needed. This means, if we get two buffers with same address, then engine * will stall. */ #define AU6601_REG_SDMA_ADDR … #define AU6601_SDMA_MASK … #define AU6601_DMA_BOUNDARY … #define AU6621_DMA_PAGE_CNT … /* PIO */ #define AU6601_REG_BUFFER … /* ADMA ctrl? AU6621 only. */ #define AU6621_DMA_CTRL … #define AU6621_DMA_ENABLE … /* CMD index */ #define AU6601_REG_CMD_OPCODE … /* CMD parametr */ #define AU6601_REG_CMD_ARG … /* CMD response 4x4 Bytes */ #define AU6601_REG_CMD_RSP0 … #define AU6601_REG_CMD_RSP1 … #define AU6601_REG_CMD_RSP2 … #define AU6601_REG_CMD_RSP3 … /* default timeout set to 125: 125 * 40ms = 5 sec * how exactly it is calculated? */ #define AU6601_TIME_OUT_CTRL … /* Block size for SDMA or PIO */ #define AU6601_REG_BLOCK_SIZE … /* Some power related reg, used together with AU6601_OUTPUT_ENABLE */ #define AU6601_POWER_CONTROL … /* PLL ctrl */ #define AU6601_CLK_SELECT … #define AU6601_CLK_OVER_CLK … #define AU6601_CLK_384_MHZ … #define AU6601_CLK_125_MHZ … #define AU6601_CLK_48_MHZ … #define AU6601_CLK_EXT_PLL … #define AU6601_CLK_X2_MODE … #define AU6601_CLK_ENABLE … #define AU6601_CLK_31_25_MHZ … #define AU6601_CLK_DIVIDER … #define AU6601_INTERFACE_MODE_CTRL … #define AU6601_DLINK_MODE … #define AU6601_INTERRUPT_DELAY_TIME … #define AU6601_SIGNAL_REQ_CTRL … #define AU6601_MS_CARD_WP … #define AU6601_SD_CARD_WP … /* same register values are used for: * - AU6601_OUTPUT_ENABLE * - AU6601_POWER_CONTROL */ #define AU6601_ACTIVE_CTRL … #define AU6601_XD_CARD … /* AU6601_MS_CARD_ACTIVE - will cativate MS card section? */ #define AU6601_MS_CARD … #define AU6601_SD_CARD … /* card slot state. It should automatically detect type of * the card */ #define AU6601_DETECT_STATUS … #define AU6601_DETECT_EN … #define AU6601_MS_DETECTED … #define AU6601_SD_DETECTED … #define AU6601_DETECT_STATUS_M … #define AU6601_REG_SW_RESET … #define AU6601_BUF_CTRL_RESET … #define AU6601_RESET_DATA … #define AU6601_RESET_CMD … #define AU6601_OUTPUT_ENABLE … #define AU6601_PAD_DRIVE0 … #define AU6601_PAD_DRIVE1 … #define AU6601_PAD_DRIVE2 … /* read EEPROM? */ #define AU6601_FUNCTION … #define AU6601_CMD_XFER_CTRL … #define AU6601_CMD_17_BYTE_CRC … #define AU6601_CMD_6_BYTE_WO_CRC … #define AU6601_CMD_6_BYTE_CRC … #define AU6601_CMD_START_XFER … #define AU6601_CMD_STOP_WAIT_RDY … #define AU6601_CMD_NO_RESP … #define AU6601_REG_BUS_CTRL … #define AU6601_BUS_WIDTH_4BIT … #define AU6601_BUS_WIDTH_8BIT … #define AU6601_BUS_WIDTH_1BIT … #define AU6601_DATA_XFER_CTRL … #define AU6601_DATA_WRITE … #define AU6601_DATA_DMA_MODE … #define AU6601_DATA_START_XFER … #define AU6601_DATA_PIN_STATE … #define AU6601_BUS_STAT_CMD … /* BIT(4) - BIT(7) are permanently 1. * May be reserved or not attached DAT4-DAT7 */ #define AU6601_BUS_STAT_DAT3 … #define AU6601_BUS_STAT_DAT2 … #define AU6601_BUS_STAT_DAT1 … #define AU6601_BUS_STAT_DAT0 … #define AU6601_BUS_STAT_DAT_MASK … #define AU6601_OPT … #define AU6601_OPT_CMD_LINE_LEVEL … #define AU6601_OPT_NCRC_16_CLK … #define AU6601_OPT_CMD_NWT … #define AU6601_OPT_STOP_CLK … #define AU6601_OPT_DDR_MODE … #define AU6601_OPT_SD_18V … #define AU6601_CLK_DELAY … #define AU6601_CLK_DATA_POSITIVE_EDGE … #define AU6601_CLK_CMD_POSITIVE_EDGE … #define AU6601_CLK_POSITIVE_EDGE_ALL … #define AU6601_REG_INT_STATUS … #define AU6601_REG_INT_ENABLE … #define AU6601_INT_DATA_END_BIT_ERR … #define AU6601_INT_DATA_CRC_ERR … #define AU6601_INT_DATA_TIMEOUT_ERR … #define AU6601_INT_CMD_INDEX_ERR … #define AU6601_INT_CMD_END_BIT_ERR … #define AU6601_INT_CMD_CRC_ERR … #define AU6601_INT_CMD_TIMEOUT_ERR … #define AU6601_INT_ERROR … #define AU6601_INT_OVER_CURRENT_ERR … #define AU6601_INT_CARD_INSERT … #define AU6601_INT_CARD_REMOVE … #define AU6601_INT_READ_BUF_RDY … #define AU6601_INT_WRITE_BUF_RDY … #define AU6601_INT_DMA_END … #define AU6601_INT_DATA_END … #define AU6601_INT_CMD_END … #define AU6601_INT_NORMAL_MASK … #define AU6601_INT_ERROR_MASK … #define AU6601_INT_CMD_MASK … #define AU6601_INT_DATA_MASK … #define AU6601_INT_ALL_MASK … /* MS_CARD mode registers */ #define AU6601_MS_STATUS … #define AU6601_MS_BUS_MODE_CTRL … #define AU6601_MS_BUS_8BIT_MODE … #define AU6601_MS_BUS_4BIT_MODE … #define AU6601_MS_BUS_1BIT_MODE … #define AU6601_MS_TPC_CMD … #define AU6601_MS_TPC_READ_PAGE_DATA … #define AU6601_MS_TPC_READ_REG … #define AU6601_MS_TPC_GET_INT … #define AU6601_MS_TPC_WRITE_PAGE_DATA … #define AU6601_MS_TPC_WRITE_REG … #define AU6601_MS_TPC_SET_RW_REG_ADRS … #define AU6601_MS_TPC_SET_CMD … #define AU6601_MS_TPC_EX_SET_CMD … #define AU6601_MS_TPC_READ_SHORT_DATA … #define AU6601_MS_TPC_WRITE_SHORT_DATA … #define AU6601_MS_TRANSFER_MODE … #define AU6601_MS_XFER_INT_TIMEOUT_CHK … #define AU6601_MS_XFER_DMA_ENABLE … #define AU6601_MS_XFER_START … #define AU6601_MS_DATA_PIN_STATE … #define AU6601_MS_INT_STATUS … #define AU6601_MS_INT_ENABLE … #define AU6601_MS_INT_OVER_CURRENT_ERROR … #define AU6601_MS_INT_DATA_CRC_ERROR … #define AU6601_MS_INT_INT_TIMEOUT … #define AU6601_MS_INT_INT_RESP_ERROR … #define AU6601_MS_INT_CED_ERROR … #define AU6601_MS_INT_TPC_TIMEOUT … #define AU6601_MS_INT_ERROR … #define AU6601_MS_INT_CARD_INSERT … #define AU6601_MS_INT_CARD_REMOVE … #define AU6601_MS_INT_BUF_READ_RDY … #define AU6601_MS_INT_BUF_WRITE_RDY … #define AU6601_MS_INT_DMA_END … #define AU6601_MS_INT_TPC_END … #define AU6601_MS_INT_DATA_MASK … #define AU6601_MS_INT_TPC_MASK … #define AU6601_MS_INT_TPC_ERROR … #define ALCOR_PCIE_LINK_CTRL_OFFSET … #define ALCOR_PCIE_LINK_CAP_OFFSET … #define ALCOR_CAP_START_OFFSET … struct alcor_dev_cfg { … }; struct alcor_pci_priv { … }; void alcor_write8(struct alcor_pci_priv *priv, u8 val, unsigned int addr); void alcor_write16(struct alcor_pci_priv *priv, u16 val, unsigned int addr); void alcor_write32(struct alcor_pci_priv *priv, u32 val, unsigned int addr); void alcor_write32be(struct alcor_pci_priv *priv, u32 val, unsigned int addr); u8 alcor_read8(struct alcor_pci_priv *priv, unsigned int addr); u32 alcor_read32(struct alcor_pci_priv *priv, unsigned int addr); u32 alcor_read32be(struct alcor_pci_priv *priv, unsigned int addr); #endif
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