// SPDX-License-Identifier: GPL-2.0 /* * Xilinx SDFEC * * Copyright (C) 2019 Xilinx, Inc. * * Description: * This driver is developed for SDFEC16 (Soft Decision FEC 16nm) * IP. It exposes a char device which supports file operations * like open(), close() and ioctl(). */ #include <linux/miscdevice.h> #include <linux/io.h> #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/poll.h> #include <linux/slab.h> #include <linux/clk.h> #include <linux/compat.h> #include <linux/highmem.h> #include <uapi/misc/xilinx_sdfec.h> #define DEV_NAME_LEN … static DEFINE_IDA(dev_nrs); /* Xilinx SDFEC Register Map */ /* CODE_WRI_PROTECT Register */ #define XSDFEC_CODE_WR_PROTECT_ADDR … /* ACTIVE Register */ #define XSDFEC_ACTIVE_ADDR … #define XSDFEC_IS_ACTIVITY_SET … /* AXIS_WIDTH Register */ #define XSDFEC_AXIS_WIDTH_ADDR … #define XSDFEC_AXIS_DOUT_WORDS_LSB … #define XSDFEC_AXIS_DOUT_WIDTH_LSB … #define XSDFEC_AXIS_DIN_WORDS_LSB … #define XSDFEC_AXIS_DIN_WIDTH_LSB … /* AXIS_ENABLE Register */ #define XSDFEC_AXIS_ENABLE_ADDR … #define XSDFEC_AXIS_OUT_ENABLE_MASK … #define XSDFEC_AXIS_IN_ENABLE_MASK … #define XSDFEC_AXIS_ENABLE_MASK … /* FEC_CODE Register */ #define XSDFEC_FEC_CODE_ADDR … /* ORDER Register Map */ #define XSDFEC_ORDER_ADDR … /* Interrupt Status Register */ #define XSDFEC_ISR_ADDR … /* Interrupt Status Register Bit Mask */ #define XSDFEC_ISR_MASK … /* Write Only - Interrupt Enable Register */ #define XSDFEC_IER_ADDR … /* Write Only - Interrupt Disable Register */ #define XSDFEC_IDR_ADDR … /* Read Only - Interrupt Mask Register */ #define XSDFEC_IMR_ADDR … /* ECC Interrupt Status Register */ #define XSDFEC_ECC_ISR_ADDR … /* Single Bit Errors */ #define XSDFEC_ECC_ISR_SBE_MASK … /* PL Initialize Single Bit Errors */ #define XSDFEC_PL_INIT_ECC_ISR_SBE_MASK … /* Multi Bit Errors */ #define XSDFEC_ECC_ISR_MBE_MASK … /* PL Initialize Multi Bit Errors */ #define XSDFEC_PL_INIT_ECC_ISR_MBE_MASK … /* Multi Bit Error to Event Shift */ #define XSDFEC_ECC_ISR_MBE_TO_EVENT_SHIFT … /* PL Initialize Multi Bit Error to Event Shift */ #define XSDFEC_PL_INIT_ECC_ISR_MBE_TO_EVENT_SHIFT … /* ECC Interrupt Status Bit Mask */ #define XSDFEC_ECC_ISR_MASK … /* ECC Interrupt Status PL Initialize Bit Mask */ #define XSDFEC_PL_INIT_ECC_ISR_MASK … /* ECC Interrupt Status All Bit Mask */ #define XSDFEC_ALL_ECC_ISR_MASK … /* ECC Interrupt Status Single Bit Errors Mask */ #define XSDFEC_ALL_ECC_ISR_SBE_MASK … /* ECC Interrupt Status Multi Bit Errors Mask */ #define XSDFEC_ALL_ECC_ISR_MBE_MASK … /* Write Only - ECC Interrupt Enable Register */ #define XSDFEC_ECC_IER_ADDR … /* Write Only - ECC Interrupt Disable Register */ #define XSDFEC_ECC_IDR_ADDR … /* Read Only - ECC Interrupt Mask Register */ #define XSDFEC_ECC_IMR_ADDR … /* BYPASS Register */ #define XSDFEC_BYPASS_ADDR … /* Turbo Code Register */ #define XSDFEC_TURBO_ADDR … #define XSDFEC_TURBO_SCALE_MASK … #define XSDFEC_TURBO_SCALE_BIT_POS … #define XSDFEC_TURBO_SCALE_MAX … /* REG0 Register */ #define XSDFEC_LDPC_CODE_REG0_ADDR_BASE … #define XSDFEC_LDPC_CODE_REG0_ADDR_HIGH … #define XSDFEC_REG0_N_MIN … #define XSDFEC_REG0_N_MAX … #define XSDFEC_REG0_N_MUL_P … #define XSDFEC_REG0_N_LSB … #define XSDFEC_REG0_K_MIN … #define XSDFEC_REG0_K_MAX … #define XSDFEC_REG0_K_MUL_P … #define XSDFEC_REG0_K_LSB … /* REG1 Register */ #define XSDFEC_LDPC_CODE_REG1_ADDR_BASE … #define XSDFEC_LDPC_CODE_REG1_ADDR_HIGH … #define XSDFEC_REG1_PSIZE_MIN … #define XSDFEC_REG1_PSIZE_MAX … #define XSDFEC_REG1_NO_PACKING_MASK … #define XSDFEC_REG1_NO_PACKING_LSB … #define XSDFEC_REG1_NM_MASK … #define XSDFEC_REG1_NM_LSB … #define XSDFEC_REG1_BYPASS_MASK … /* REG2 Register */ #define XSDFEC_LDPC_CODE_REG2_ADDR_BASE … #define XSDFEC_LDPC_CODE_REG2_ADDR_HIGH … #define XSDFEC_REG2_NLAYERS_MIN … #define XSDFEC_REG2_NLAYERS_MAX … #define XSDFEC_REG2_NNMQC_MASK … #define XSDFEC_REG2_NMQC_LSB … #define XSDFEC_REG2_NORM_TYPE_MASK … #define XSDFEC_REG2_NORM_TYPE_LSB … #define XSDFEC_REG2_SPECIAL_QC_MASK … #define XSDFEC_REG2_SPEICAL_QC_LSB … #define XSDFEC_REG2_NO_FINAL_PARITY_MASK … #define XSDFEC_REG2_NO_FINAL_PARITY_LSB … #define XSDFEC_REG2_MAX_SCHEDULE_MASK … #define XSDFEC_REG2_MAX_SCHEDULE_LSB … /* REG3 Register */ #define XSDFEC_LDPC_CODE_REG3_ADDR_BASE … #define XSDFEC_LDPC_CODE_REG3_ADDR_HIGH … #define XSDFEC_REG3_LA_OFF_LSB … #define XSDFEC_REG3_QC_OFF_LSB … #define XSDFEC_LDPC_REG_JUMP … #define XSDFEC_REG_WIDTH_JUMP … /* The maximum number of pinned pages */ #define MAX_NUM_PAGES … /** * struct xsdfec_clks - For managing SD-FEC clocks * @core_clk: Main processing clock for core * @axi_clk: AXI4-Lite memory-mapped clock * @din_words_clk: DIN Words AXI4-Stream Slave clock * @din_clk: DIN AXI4-Stream Slave clock * @dout_clk: DOUT Words AXI4-Stream Slave clock * @dout_words_clk: DOUT AXI4-Stream Slave clock * @ctrl_clk: Control AXI4-Stream Slave clock * @status_clk: Status AXI4-Stream Slave clock */ struct xsdfec_clks { … }; /** * struct xsdfec_dev - Driver data for SDFEC * @miscdev: Misc device handle * @clks: Clocks managed by the SDFEC driver * @waitq: Driver wait queue * @config: Configuration of the SDFEC device * @dev_name: Device name * @flags: spinlock flags * @regs: device physical base address * @dev: pointer to device struct * @state: State of the SDFEC device * @error_data_lock: Error counter and states spinlock * @dev_id: Device ID * @isr_err_count: Count of ISR errors * @cecc_count: Count of Correctable ECC errors (SBE) * @uecc_count: Count of Uncorrectable ECC errors (MBE) * @irq: IRQ number * @state_updated: indicates State updated by interrupt handler * @stats_updated: indicates Stats updated by interrupt handler * @intr_enabled: indicates IRQ enabled * * This structure contains necessary state for SDFEC driver to operate */ struct xsdfec_dev { … }; static inline void xsdfec_regwrite(struct xsdfec_dev *xsdfec, u32 addr, u32 value) { … } static inline u32 xsdfec_regread(struct xsdfec_dev *xsdfec, u32 addr) { … } static void update_bool_config_from_reg(struct xsdfec_dev *xsdfec, u32 reg_offset, u32 bit_num, char *config_value) { … } static void update_config_from_hw(struct xsdfec_dev *xsdfec) { … } static int xsdfec_get_status(struct xsdfec_dev *xsdfec, void __user *arg) { … } static int xsdfec_get_config(struct xsdfec_dev *xsdfec, void __user *arg) { … } static int xsdfec_isr_enable(struct xsdfec_dev *xsdfec, bool enable) { … } static int xsdfec_ecc_isr_enable(struct xsdfec_dev *xsdfec, bool enable) { … } static int xsdfec_set_irq(struct xsdfec_dev *xsdfec, void __user *arg) { … } static int xsdfec_set_turbo(struct xsdfec_dev *xsdfec, void __user *arg) { … } static int xsdfec_get_turbo(struct xsdfec_dev *xsdfec, void __user *arg) { … } static int xsdfec_reg0_write(struct xsdfec_dev *xsdfec, u32 n, u32 k, u32 psize, u32 offset) { … } static int xsdfec_reg1_write(struct xsdfec_dev *xsdfec, u32 psize, u32 no_packing, u32 nm, u32 offset) { … } static int xsdfec_reg2_write(struct xsdfec_dev *xsdfec, u32 nlayers, u32 nmqc, u32 norm_type, u32 special_qc, u32 no_final_parity, u32 max_schedule, u32 offset) { … } static int xsdfec_reg3_write(struct xsdfec_dev *xsdfec, u8 sc_off, u8 la_off, u16 qc_off, u32 offset) { … } static int xsdfec_table_write(struct xsdfec_dev *xsdfec, u32 offset, u32 *src_ptr, u32 len, const u32 base_addr, const u32 depth) { … } static int xsdfec_add_ldpc(struct xsdfec_dev *xsdfec, void __user *arg) { … } static int xsdfec_set_order(struct xsdfec_dev *xsdfec, void __user *arg) { … } static int xsdfec_set_bypass(struct xsdfec_dev *xsdfec, bool __user *arg) { … } static int xsdfec_is_active(struct xsdfec_dev *xsdfec, bool __user *arg) { … } static u32 xsdfec_translate_axis_width_cfg_val(enum xsdfec_axis_width axis_width_cfg) { … } static u32 xsdfec_translate_axis_words_cfg_val(enum xsdfec_axis_word_include axis_word_inc_cfg) { … } static int xsdfec_cfg_axi_streams(struct xsdfec_dev *xsdfec) { … } static int xsdfec_start(struct xsdfec_dev *xsdfec) { … } static int xsdfec_stop(struct xsdfec_dev *xsdfec) { … } static int xsdfec_clear_stats(struct xsdfec_dev *xsdfec) { … } static int xsdfec_get_stats(struct xsdfec_dev *xsdfec, void __user *arg) { … } static int xsdfec_set_default_config(struct xsdfec_dev *xsdfec) { … } static long xsdfec_dev_ioctl(struct file *fptr, unsigned int cmd, unsigned long data) { … } static __poll_t xsdfec_poll(struct file *file, poll_table *wait) { … } static const struct file_operations xsdfec_fops = …; static int xsdfec_parse_of(struct xsdfec_dev *xsdfec) { … } static irqreturn_t xsdfec_irq_thread(int irq, void *dev_id) { … } static int xsdfec_clk_init(struct platform_device *pdev, struct xsdfec_clks *clks) { … } static void xsdfec_disable_all_clks(struct xsdfec_clks *clks) { … } static int xsdfec_probe(struct platform_device *pdev) { … } static void xsdfec_remove(struct platform_device *pdev) { … } static const struct of_device_id xsdfec_of_match[] = …; MODULE_DEVICE_TABLE(of, xsdfec_of_match); static struct platform_driver xsdfec_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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