linux/include/linux/mfd/lp87565.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Functions to access LP87565 power management chip.
 *
 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
 */

#ifndef __LINUX_MFD_LP87565_H
#define __LINUX_MFD_LP87565_H

#include <linux/i2c.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>

enum lp87565_device_type {};

/* All register addresses */
#define LP87565_REG_DEV_REV
#define LP87565_REG_OTP_REV
#define LP87565_REG_BUCK0_CTRL_1
#define LP87565_REG_BUCK0_CTRL_2

#define LP87565_REG_BUCK1_CTRL_1
#define LP87565_REG_BUCK1_CTRL_2

#define LP87565_REG_BUCK2_CTRL_1
#define LP87565_REG_BUCK2_CTRL_2

#define LP87565_REG_BUCK3_CTRL_1
#define LP87565_REG_BUCK3_CTRL_2

#define LP87565_REG_BUCK0_VOUT
#define LP87565_REG_BUCK0_FLOOR_VOUT

#define LP87565_REG_BUCK1_VOUT
#define LP87565_REG_BUCK1_FLOOR_VOUT

#define LP87565_REG_BUCK2_VOUT
#define LP87565_REG_BUCK2_FLOOR_VOUT

#define LP87565_REG_BUCK3_VOUT
#define LP87565_REG_BUCK3_FLOOR_VOUT

#define LP87565_REG_BUCK0_DELAY
#define LP87565_REG_BUCK1_DELAY

#define LP87565_REG_BUCK2_DELAY
#define LP87565_REG_BUCK3_DELAY

#define LP87565_REG_GPO2_DELAY
#define LP87565_REG_GPO3_DELAY
#define LP87565_REG_RESET
#define LP87565_REG_CONFIG

#define LP87565_REG_INT_TOP_1
#define LP87565_REG_INT_TOP_2

#define LP87565_REG_INT_BUCK_0_1
#define LP87565_REG_INT_BUCK_2_3
#define LP87565_REG_TOP_STAT
#define LP87565_REG_BUCK_0_1_STAT
#define LP87565_REG_BUCK_2_3_STAT

#define LP87565_REG_TOP_MASK_1
#define LP87565_REG_TOP_MASK_2

#define LP87565_REG_BUCK_0_1_MASK
#define LP87565_REG_BUCK_2_3_MASK
#define LP87565_REG_SEL_I_LOAD

#define LP87565_REG_I_LOAD_2
#define LP87565_REG_I_LOAD_1

#define LP87565_REG_PGOOD_CTRL1
#define LP87565_REG_PGOOD_CTRL2
#define LP87565_REG_PGOOD_FLT
#define LP87565_REG_PLL_CTRL
#define LP87565_REG_PIN_FUNCTION
#define LP87565_REG_GPIO_CONFIG
#define LP87565_REG_GPIO_IN
#define LP87565_REG_GPIO_OUT

#define LP87565_REG_MAX

/* Register field definitions */
#define LP87565_DEV_REV_DEV_ID
#define LP87565_DEV_REV_ALL_LAYER
#define LP87565_DEV_REV_METAL_LAYER

#define LP87565_OTP_REV_OTP_ID

#define LP87565_BUCK_CTRL_1_EN
#define LP87565_BUCK_CTRL_1_EN_PIN_CTRL
#define LP87565_BUCK_CTRL_1_PIN_SELECT_EN

#define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN
#define LP87565_BUCK_CTRL_1_RDIS_EN
#define LP87565_BUCK_CTRL_1_FPWM
/* Bit0 is reserved for BUCK1 and BUCK3 and valid only for BUCK0 and BUCK2 */
#define LP87565_BUCK_CTRL_1_FPWM_MP_0_2

#define LP87565_BUCK_CTRL_2_ILIM
#define LP87565_BUCK_CTRL_2_SLEW_RATE

#define LP87565_BUCK_VSET
#define LP87565_BUCK_FLOOR_VSET

#define LP87565_BUCK_SHUTDOWN_DELAY
#define LP87565_BUCK_STARTUP_DELAY

#define LP87565_GPIO_SHUTDOWN_DELAY
#define LP87565_GPIO_STARTUP_DELAY

#define LP87565_RESET_SW_RESET

#define LP87565_CONFIG_DOUBLE_DELAY
#define LP87565_CONFIG_CLKIN_PD
#define LP87565_CONFIG_EN4_PD
#define LP87565_CONFIG_EN3_PD
#define LP87565_CONFIG_TDIE_WARN_LEVEL
#define LP87565_CONFIG_EN2_PD
#define LP87565_CONFIG_EN1_PD

#define LP87565_INT_GPIO
#define LP87565_INT_BUCK23
#define LP87565_INT_BUCK01
#define LP87565_NO_SYNC_CLK
#define LP87565_TDIE_SD
#define LP87565_TDIE_WARN
#define LP87565_INT_OVP
#define LP87565_I_LOAD_READY

#define LP87565_INT_TOP2_RESET_REG

#define LP87565_BUCK1_PG_INT
#define LP87565_BUCK1_SC_INT
#define LP87565_BUCK1_ILIM_INT
#define LP87565_BUCK0_PG_INT
#define LP87565_BUCK0_SC_INT
#define LP87565_BUCK0_ILIM_INT

#define LP87565_BUCK3_PG_INT
#define LP87565_BUCK3_SC_INT
#define LP87565_BUCK3_ILIM_INT
#define LP87565_BUCK2_PG_INT
#define LP87565_BUCK2_SC_INT
#define LP87565_BUCK2_ILIM_INT

#define LP87565_SYNC_CLK_STAT
#define LP87565_TDIE_SD_STAT
#define LP87565_TDIE_WARN_STAT
#define LP87565_OVP_STAT

#define LP87565_BUCK1_STAT
#define LP87565_BUCK1_PG_STAT
#define LP87565_BUCK1_ILIM_STAT
#define LP87565_BUCK0_STAT
#define LP87565_BUCK0_PG_STAT
#define LP87565_BUCK0_ILIM_STAT

#define LP87565_BUCK3_STAT
#define LP87565_BUCK3_PG_STAT
#define LP87565_BUCK3_ILIM_STAT
#define LP87565_BUCK2_STAT
#define LP87565_BUCK2_PG_STAT
#define LP87565_BUCK2_ILIM_STAT

#define LPL87565_GPIO_MASK
#define LPL87565_SYNC_CLK_MASK
#define LPL87565_TDIE_WARN_MASK
#define LPL87565_I_LOAD_READY_MASK

#define LPL87565_RESET_REG_MASK

#define LPL87565_BUCK1_PG_MASK
#define LPL87565_BUCK1_ILIM_MASK
#define LPL87565_BUCK0_PG_MASK
#define LPL87565_BUCK0_ILIM_MASK

#define LPL87565_BUCK3_PG_MASK
#define LPL87565_BUCK3_ILIM_MASK
#define LPL87565_BUCK2_PG_MASK
#define LPL87565_BUCK2_ILIM_MASK

#define LP87565_LOAD_CURRENT_BUCK_SELECT

#define LP87565_I_LOAD2_BUCK_LOAD_CURRENT
#define LP87565_I_LOAD1_BUCK_LOAD_CURRENT

#define LP87565_PG3_SEL
#define LP87565_PG2_SEL
#define LP87565_PG1_SEL
#define LP87565_PG0_SEL

#define LP87565_HALF_DAY
#define LP87565_EN_PG0_NINT
#define LP87565_PGOOD_SET_DELAY
#define LP87565_EN_PGFLT_STAT
#define LP87565_PGOOD_WINDOW
#define LP87565_PGOOD_OD
#define LP87565_PGOOD_POL

#define LP87565_PG3_FLT
#define LP87565_PG2_FLT
#define LP87565_PG1_FLT
#define LP87565_PG0_FLT

#define LP87565_PLL_MODE
#define LP87565_EXT_CLK_FREQ

#define LP87565_EN_SPREAD_SPEC
#define LP87565_EN_PIN_CTRL_GPIO3
#define LP87565_EN_PIN_SELECT_GPIO3
#define LP87565_EN_PIN_CTRL_GPIO2
#define LP87565_EN_PIN_SELECT_GPIO2
#define LP87565_GPIO3_SEL
#define LP87565_GPIO2_SEL
#define LP87565_GPIO1_SEL

#define LP87565_GPIO3_OD
#define LP87565_GPIO2_OD
#define LP87565_GPIO1_OD
#define LP87565_GPIO3_DIR
#define LP87565_GPIO2_DIR
#define LP87565_GPIO1_DIR

#define LP87565_GPIO3_IN
#define LP87565_GPIO2_IN
#define LP87565_GPIO1_IN

#define LP87565_GPIO3_OUT
#define LP87565_GPIO2_OUT
#define LP87565_GPIO1_OUT

/**
 * struct LP87565 - state holder for the LP87565 driver
 * @dev: struct device pointer for MFD device
 * @rev: revision of the LP87565
 * @dev_type: The device type for example lp87565-q1
 * @lock: lock guarding the data structure
 * @regmap: register map of the LP87565 PMIC
 *
 * Device data may be used to access the LP87565 chip
 */
struct lp87565 {};
#endif /* __LINUX_MFD_LP87565_H */