// SPDX-License-Identifier: GPL-2.0-only /* * lpc_ich.c - LPC interface for Intel ICH * * LPC bridge function of the Intel ICH contains many other * functional units, such as Interrupt controllers, Timers, * Power Management, System Management, GPIO, RTC, and LPC * Configuration Registers. * * This driver is derived from lpc_sch. * * Copyright (c) 2017, 2021-2022 Intel Corporation * Copyright (c) 2011 Extreme Engineering Solution, Inc. * Author: Aaron Sierra <[email protected]> * * This driver supports the following I/O Controller hubs: * (See the intel documentation on http://developer.intel.com.) * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) * document number 290687-002, 298242-027: 82801BA (ICH2) * document number 290733-003, 290739-013: 82801CA (ICH3-S) * document number 290716-001, 290718-007: 82801CAM (ICH3-M) * document number 290744-001, 290745-025: 82801DB (ICH4) * document number 252337-001, 252663-008: 82801DBM (ICH4-M) * document number 273599-001, 273645-002: 82801E (C-ICH) * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) * document number 300641-004, 300884-013: 6300ESB * document number 301473-002, 301474-026: 82801F (ICH6) * document number 313082-001, 313075-006: 631xESB, 632xESB * document number 307013-003, 307014-024: 82801G (ICH7) * document number 322896-001, 322897-001: NM10 * document number 313056-003, 313057-017: 82801H (ICH8) * document number 316972-004, 316973-012: 82801I (ICH9) * document number 319973-002, 319974-002: 82801J (ICH10) * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) * document number 320066-003, 320257-008: EP80597 (IICH) * document number 324645-001, 324646-001: Cougar Point (CPT) */ #define pr_fmt(fmt) … #include <linux/align.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/errno.h> #include <linux/acpi.h> #include <linux/pci.h> #include <linux/pinctrl/pinctrl.h> #include <linux/mfd/core.h> #include <linux/mfd/lpc_ich.h> #include <linux/platform_data/itco_wdt.h> #include <linux/platform_data/x86/p2sb.h> #define ACPIBASE … #define ACPIBASE_GPE_OFF … #define ACPIBASE_GPE_END … #define ACPIBASE_SMI_OFF … #define ACPIBASE_SMI_END … #define ACPIBASE_PMC_OFF … #define ACPIBASE_PMC_END … #define ACPIBASE_TCO_OFF … #define ACPIBASE_TCO_END … #define ACPICTRL_PMCBASE … #define ACPIBASE_GCS_OFF … #define ACPIBASE_GCS_END … #define SPIBASE_BYT … #define SPIBASE_BYT_SZ … #define SPIBASE_BYT_EN … #define BYT_BCR … #define BYT_BCR_WPD … #define SPIBASE_LPT … #define SPIBASE_LPT_SZ … #define BCR … #define BCR_WPD … #define GPIOBASE_ICH0 … #define GPIOCTRL_ICH0 … #define GPIOBASE_ICH6 … #define GPIOCTRL_ICH6 … #define RCBABASE … #define wdt_io_res(i) … #define wdt_mem_res(i) … #define wdt_res(b, i) … static struct resource wdt_ich_res[] = …; static struct resource gpio_ich_res[] = …; static struct resource intel_spi_res[] = …; static struct mfd_cell lpc_ich_wdt_cell = …; static struct mfd_cell lpc_ich_gpio_cell = …; #define INTEL_GPIO_RESOURCE_SIZE … struct lpc_ich_gpio_info { … }; #define APL_GPIO_NORTH … #define APL_GPIO_NORTHWEST … #define APL_GPIO_WEST … #define APL_GPIO_SOUTHWEST … #define APL_GPIO_NR_DEVICES … #define APL_GPIO_NR_RESOURCES … /* Offset data for Apollo Lake GPIO controllers */ static const resource_size_t apl_gpio_offsets[APL_GPIO_NR_RESOURCES] = …; #define APL_GPIO_IRQ … static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = …; static struct resource *apl_gpio_mem_resources[APL_GPIO_NR_RESOURCES] = …; static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = …; static const struct lpc_ich_gpio_info apl_gpio_info = …; #define DNV_GPIO_NORTH … #define DNV_GPIO_SOUTH … #define DNV_GPIO_NR_DEVICES … #define DNV_GPIO_NR_RESOURCES … /* Offset data for Denverton GPIO controllers */ static const resource_size_t dnv_gpio_offsets[DNV_GPIO_NR_RESOURCES] = …; #define DNV_GPIO_IRQ … static struct resource dnv_gpio_resources[DNV_GPIO_NR_RESOURCES + 1] = …; static struct resource *dnv_gpio_mem_resources[DNV_GPIO_NR_RESOURCES] = …; static const struct mfd_cell dnv_gpio_devices[DNV_GPIO_NR_DEVICES] = …; static const struct lpc_ich_gpio_info dnv_gpio_info = …; static struct mfd_cell lpc_ich_spi_cell = …; /* chipset related info */ enum lpc_chipsets { … }; struct lpc_ich_priv { … }; static struct lpc_ich_info lpc_chipset_info[] = …; /* * This data only exists for exporting the supported PCI ids * via MODULE_DEVICE_TABLE. We do not actually register a * pci_driver, because the I/O Controller Hub has also other * functions that probably will be registered by other drivers. */ static const struct pci_device_id lpc_ich_ids[] = …; MODULE_DEVICE_TABLE(pci, lpc_ich_ids); static void lpc_ich_restore_config_space(struct pci_dev *dev) { … } static void lpc_ich_enable_acpi_space(struct pci_dev *dev) { … } static void lpc_ich_enable_gpio_space(struct pci_dev *dev) { … } static void lpc_ich_enable_pmc_space(struct pci_dev *dev) { … } static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev) { … } static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev) { … } /* * We don't check for resource conflict globally. There are 2 or 3 independent * GPIO groups and it's enough to have access to one of these to instantiate * the device. */ static int lpc_ich_check_conflict_gpio(struct resource *res) { … } static int lpc_ich_init_gpio(struct pci_dev *dev) { … } static int lpc_ich_init_wdt(struct pci_dev *dev) { … } static int lpc_ich_init_pinctrl(struct pci_dev *dev) { … } static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data) { … } static bool lpc_ich_set_writeable(struct pci_bus *bus, unsigned int devfn) { … } static bool lpc_ich_lpt_set_writeable(void __iomem *base, void *data) { … } static bool lpc_ich_bxt_set_writeable(void __iomem *base, void *data) { … } static int lpc_ich_init_spi(struct pci_dev *dev) { … } static int lpc_ich_probe(struct pci_dev *dev, const struct pci_device_id *id) { … } static void lpc_ich_remove(struct pci_dev *dev) { … } static struct pci_driver lpc_ich_driver = …; module_pci_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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