linux/drivers/gpio/gpio-mlxbf3.c

// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
/* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */

#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/types.h>

/*
 * There are 2 YU GPIO blocks:
 * gpio[0]: HOST_GPIO0->HOST_GPIO31
 * gpio[1]: HOST_GPIO32->HOST_GPIO55
 */
#define MLXBF3_GPIO_MAX_PINS_PER_BLOCK …
#define MLXBF3_GPIO_MAX_PINS_BLOCK0 …
#define MLXBF3_GPIO_MAX_PINS_BLOCK1 …

/*
 * fw_gpio[x] block registers and their offset
 */
#define MLXBF_GPIO_FW_OUTPUT_ENABLE_SET …
#define MLXBF_GPIO_FW_DATA_OUT_SET …

#define MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR …
#define MLXBF_GPIO_FW_DATA_OUT_CLEAR …

#define MLXBF_GPIO_CAUSE_RISE_EN …
#define MLXBF_GPIO_CAUSE_FALL_EN …
#define MLXBF_GPIO_READ_DATA_IN …

#define MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0 …
#define MLXBF_GPIO_CAUSE_OR_EVTEN0 …
#define MLXBF_GPIO_CAUSE_OR_CLRCAUSE …

struct mlxbf3_gpio_context { … };

static void mlxbf3_gpio_irq_enable(struct irq_data *irqd)
{ … }

static void mlxbf3_gpio_irq_disable(struct irq_data *irqd)
{ … }

static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr)
{ … }

static int
mlxbf3_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
{ … }

/* This function needs to be defined for handle_edge_irq() */
static void mlxbf3_gpio_irq_ack(struct irq_data *data)
{ … }

static const struct irq_chip gpio_mlxbf3_irqchip = …;

static int mlxbf3_gpio_add_pin_ranges(struct gpio_chip *chip)
{ … }

static int mlxbf3_gpio_probe(struct platform_device *pdev)
{ … }

static const struct acpi_device_id mlxbf3_gpio_acpi_match[] = …;
MODULE_DEVICE_TABLE(acpi, mlxbf3_gpio_acpi_match);

static struct platform_driver mlxbf3_gpio_driver = …;
module_platform_driver(…) …;

MODULE_SOFTDEP(…) …;
MODULE_DESCRIPTION(…) …;
MODULE_AUTHOR(…) …;
MODULE_LICENSE(…) …;