/* SPDX-License-Identifier: GPL-2.0 */ /* * Intel MAX 10 Board Management Controller chip. * * Copyright (C) 2018-2020 Intel Corporation, Inc. */ #ifndef __MFD_INTEL_M10_BMC_H #define __MFD_INTEL_M10_BMC_H #include <linux/bitfield.h> #include <linux/bits.h> #include <linux/dev_printk.h> #include <linux/regmap.h> #include <linux/rwsem.h> #define M10BMC_N3000_LEGACY_BUILD_VER … #define M10BMC_N3000_SYS_BASE … #define M10BMC_N3000_SYS_END … #define M10BMC_N3000_FLASH_BASE … #define M10BMC_N3000_FLASH_END … #define M10BMC_N3000_MEM_END … #define M10BMC_STAGING_BASE … #define M10BMC_STAGING_SIZE … /* Register offset of system registers */ #define NIOS2_N3000_FW_VERSION … #define M10BMC_N3000_MAC_LOW … #define M10BMC_N3000_MAC_BYTE4 … #define M10BMC_N3000_MAC_BYTE3 … #define M10BMC_N3000_MAC_BYTE2 … #define M10BMC_N3000_MAC_BYTE1 … #define M10BMC_N3000_MAC_HIGH … #define M10BMC_N3000_MAC_BYTE6 … #define M10BMC_N3000_MAC_BYTE5 … #define M10BMC_N3000_MAC_COUNT … #define M10BMC_N3000_TEST_REG … #define M10BMC_N3000_BUILD_VER … #define M10BMC_N3000_VER_MAJOR_MSK … #define M10BMC_N3000_VER_PCB_INFO_MSK … #define M10BMC_N3000_VER_LEGACY_INVALID … /* Telemetry registers */ #define M10BMC_N3000_TELEM_START … #define M10BMC_N3000_TELEM_END … #define M10BMC_D5005_TELEM_END … /* Secure update doorbell register, in system register region */ #define M10BMC_N3000_DOORBELL … /* Authorization Result register, in system register region */ #define M10BMC_N3000_AUTH_RESULT … /* Doorbell register fields */ #define DRBL_RSU_REQUEST … #define DRBL_RSU_PROGRESS … #define DRBL_HOST_STATUS … #define DRBL_RSU_STATUS … #define DRBL_PKVL_EEPROM_LOAD_SEC … #define DRBL_PKVL1_POLL_EN … #define DRBL_PKVL2_POLL_EN … #define DRBL_CONFIG_SEL … #define DRBL_REBOOT_REQ … #define DRBL_REBOOT_DISABLED … /* Progress states */ #define RSU_PROG_IDLE … #define RSU_PROG_PREPARE … #define RSU_PROG_READY … #define RSU_PROG_AUTHENTICATING … #define RSU_PROG_COPYING … #define RSU_PROG_UPDATE_CANCEL … #define RSU_PROG_PROGRAM_KEY_HASH … #define RSU_PROG_RSU_DONE … #define RSU_PROG_PKVL_PROM_DONE … /* Device and error states */ #define RSU_STAT_NORMAL … #define RSU_STAT_TIMEOUT … #define RSU_STAT_AUTH_FAIL … #define RSU_STAT_COPY_FAIL … #define RSU_STAT_FATAL … #define RSU_STAT_PKVL_REJECT … #define RSU_STAT_NON_INC … #define RSU_STAT_ERASE_FAIL … #define RSU_STAT_WEAROUT … #define RSU_STAT_NIOS_OK … #define RSU_STAT_USER_OK … #define RSU_STAT_FACTORY_OK … #define RSU_STAT_USER_FAIL … #define RSU_STAT_FACTORY_FAIL … #define RSU_STAT_NIOS_FLASH_ERR … #define RSU_STAT_FPGA_FLASH_ERR … #define HOST_STATUS_IDLE … #define HOST_STATUS_WRITE_DONE … #define HOST_STATUS_ABORT_RSU … #define rsu_prog(doorbell) … /* interval 100ms and timeout 5s */ #define NIOS_HANDSHAKE_INTERVAL_US … #define NIOS_HANDSHAKE_TIMEOUT_US … /* RSU PREP Timeout (2 minutes) to erase flash staging area */ #define RSU_PREP_INTERVAL_MS … #define RSU_PREP_TIMEOUT_MS … /* RSU Complete Timeout (40 minutes) for full flash update */ #define RSU_COMPLETE_INTERVAL_MS … #define RSU_COMPLETE_TIMEOUT_MS … /* Addresses for security related data in FLASH */ #define M10BMC_N3000_BMC_REH_ADDR … #define M10BMC_N3000_BMC_PROG_ADDR … #define M10BMC_N3000_BMC_PROG_MAGIC … #define M10BMC_N3000_SR_REH_ADDR … #define M10BMC_N3000_SR_PROG_ADDR … #define M10BMC_N3000_SR_PROG_MAGIC … #define M10BMC_N3000_PR_REH_ADDR … #define M10BMC_N3000_PR_PROG_ADDR … #define M10BMC_N3000_PR_PROG_MAGIC … /* Address of 4KB inverted bit vector containing staging area FLASH count */ #define M10BMC_N3000_STAGING_FLASH_COUNT … #define M10BMC_N6000_INDIRECT_BASE … #define M10BMC_N6000_SYS_BASE … #define M10BMC_N6000_SYS_END … #define M10BMC_N6000_DOORBELL … #define M10BMC_N6000_AUTH_RESULT … #define AUTH_RESULT_RSU_STATUS … #define M10BMC_N6000_BUILD_VER … #define NIOS2_N6000_FW_VERSION … #define M10BMC_N6000_MAC_LOW … #define M10BMC_N6000_MAC_HIGH … /* Addresses for security related data in FLASH */ #define M10BMC_N6000_BMC_REH_ADDR … #define M10BMC_N6000_BMC_PROG_ADDR … #define M10BMC_N6000_BMC_PROG_MAGIC … #define M10BMC_N6000_SR_REH_ADDR … #define M10BMC_N6000_SR_PROG_ADDR … #define M10BMC_N6000_SR_PROG_MAGIC … #define M10BMC_N6000_PR_REH_ADDR … #define M10BMC_N6000_PR_PROG_ADDR … #define M10BMC_N6000_PR_PROG_MAGIC … #define M10BMC_N6000_STAGING_FLASH_COUNT … #define M10BMC_N6000_FLASH_MUX_CTRL … #define M10BMC_N6000_FLASH_MUX_SELECTION … #define M10BMC_N6000_FLASH_MUX_IDLE … #define M10BMC_N6000_FLASH_MUX_NIOS … #define M10BMC_N6000_FLASH_MUX_HOST … #define M10BMC_N6000_FLASH_MUX_PFL … #define get_flash_mux(mux) … #define M10BMC_N6000_FLASH_NIOS_REQUEST … #define M10BMC_N6000_FLASH_HOST_REQUEST … #define M10BMC_N6000_FLASH_CTRL … #define M10BMC_N6000_FLASH_WR_MODE … #define M10BMC_N6000_FLASH_RD_MODE … #define M10BMC_N6000_FLASH_BUSY … #define M10BMC_N6000_FLASH_FIFO_SPACE … #define M10BMC_N6000_FLASH_READ_COUNT … #define M10BMC_N6000_FLASH_ADDR … #define M10BMC_N6000_FLASH_FIFO … #define M10BMC_N6000_READ_BLOCK_SIZE … #define M10BMC_N6000_FIFO_MAX_BYTES … #define M10BMC_N6000_FIFO_WORD_SIZE … #define M10BMC_N6000_FIFO_MAX_WORDS … #define M10BMC_FLASH_INT_US … #define M10BMC_FLASH_TIMEOUT_US … /** * struct m10bmc_csr_map - Intel MAX 10 BMC CSR register map */ struct m10bmc_csr_map { … }; /** * struct intel_m10bmc_platform_info - Intel MAX 10 BMC platform specific information * @cells: MFD cells * @n_cells: MFD cells ARRAY_SIZE() * @handshake_sys_reg_ranges: array of register ranges for fw handshake regs * @handshake_sys_reg_nranges: number of register ranges for fw handshake regs * @csr_map: the mappings for register definition of MAX10 BMC */ struct intel_m10bmc_platform_info { … }; struct intel_m10bmc; /** * struct intel_m10bmc_flash_bulk_ops - device specific operations for flash R/W * @read: read a block of data from flash * @write: write a block of data to flash * @lock_write: locks flash access for erase+write * @unlock_write: unlock flash access * * Write must be protected with @lock_write and @unlock_write. While the flash * is locked, @read returns -EBUSY. */ struct intel_m10bmc_flash_bulk_ops { … }; enum m10bmc_fw_state { … }; /** * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure * @dev: this device * @regmap: the regmap used to access registers by m10bmc itself * @info: the platform information for MAX10 BMC * @flash_bulk_ops: optional device specific operations for flash R/W * @bmcfw_lock: read/write semaphore to BMC firmware running state * @bmcfw_state: BMC firmware running state. Available only when * handshake_sys_reg_nranges > 0. */ struct intel_m10bmc { … }; /* * register access helper functions. * * m10bmc_raw_read - read m10bmc register per addr * m10bmc_sys_read - read m10bmc system register per offset * m10bmc_sys_update_bits - update m10bmc system register per offset */ static inline int m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr, unsigned int *val) { … } int m10bmc_sys_read(struct intel_m10bmc *m10bmc, unsigned int offset, unsigned int *val); int m10bmc_sys_update_bits(struct intel_m10bmc *m10bmc, unsigned int offset, unsigned int msk, unsigned int val); /* * Track the state of the firmware, as it is not available for register * handshakes during secure updates on some MAX 10 cards. */ void m10bmc_fw_state_set(struct intel_m10bmc *m10bmc, enum m10bmc_fw_state new_state); /* * MAX10 BMC Core support */ int m10bmc_dev_init(struct intel_m10bmc *m10bmc, const struct intel_m10bmc_platform_info *info); extern const struct attribute_group *m10bmc_dev_groups[]; #endif /* __MFD_INTEL_M10_BMC_H */
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