/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright(c) 2020 Intel Corporation. */ #ifndef __CXL_H__ #define __CXL_H__ #include <linux/libnvdimm.h> #include <linux/bitfield.h> #include <linux/notifier.h> #include <linux/bitops.h> #include <linux/log2.h> #include <linux/node.h> #include <linux/io.h> extern const struct nvdimm_security_ops *cxl_security_ops; /** * DOC: cxl objects * * The CXL core objects like ports, decoders, and regions are shared * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers * (port-driver, region-driver, nvdimm object-drivers... etc). */ /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ #define CXL_COMPONENT_REG_BLOCK_SIZE … /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ #define CXL_CM_OFFSET … #define CXL_CM_CAP_HDR_OFFSET … #define CXL_CM_CAP_HDR_ID_MASK … #define CM_CAP_HDR_CAP_ID … #define CXL_CM_CAP_HDR_VERSION_MASK … #define CM_CAP_HDR_CAP_VERSION … #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK … #define CM_CAP_HDR_CACHE_MEM_VERSION … #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK … #define CXL_CM_CAP_PTR_MASK … #define CXL_CM_CAP_CAP_ID_RAS … #define CXL_CM_CAP_CAP_ID_HDM … #define CXL_CM_CAP_CAP_HDM_VERSION … /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ #define CXL_HDM_DECODER_CAP_OFFSET … #define CXL_HDM_DECODER_COUNT_MASK … #define CXL_HDM_DECODER_TARGET_COUNT_MASK … #define CXL_HDM_DECODER_INTERLEAVE_11_8 … #define CXL_HDM_DECODER_INTERLEAVE_14_12 … #define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY … #define CXL_HDM_DECODER_INTERLEAVE_16_WAY … #define CXL_HDM_DECODER_CTRL_OFFSET … #define CXL_HDM_DECODER_ENABLE … #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) … #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) … #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) … #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) … #define CXL_HDM_DECODER0_CTRL_OFFSET(i) … #define CXL_HDM_DECODER0_CTRL_IG_MASK … #define CXL_HDM_DECODER0_CTRL_IW_MASK … #define CXL_HDM_DECODER0_CTRL_LOCK … #define CXL_HDM_DECODER0_CTRL_COMMIT … #define CXL_HDM_DECODER0_CTRL_COMMITTED … #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR … #define CXL_HDM_DECODER0_CTRL_HOSTONLY … #define CXL_HDM_DECODER0_TL_LOW(i) … #define CXL_HDM_DECODER0_TL_HIGH(i) … #define CXL_HDM_DECODER0_SKIP_LOW(i) … #define CXL_HDM_DECODER0_SKIP_HIGH(i) … /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ #define CXL_DECODER_MIN_GRANULARITY … #define CXL_DECODER_MAX_ENCODED_IG … static inline int cxl_hdm_decoder_count(u32 cap_hdr) { … } /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ static inline int eig_to_granularity(u16 eig, unsigned int *granularity) { … } /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ static inline int eiw_to_ways(u8 eiw, unsigned int *ways) { … } static inline int granularity_to_eig(int granularity, u16 *eig) { … } static inline int ways_to_eiw(unsigned int ways, u8 *eiw) { … } /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET … #define CXL_RAS_UNCORRECTABLE_STATUS_MASK … #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET … #define CXL_RAS_UNCORRECTABLE_MASK_MASK … #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK … #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET … #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK … #define CXL_RAS_CORRECTABLE_STATUS_OFFSET … #define CXL_RAS_CORRECTABLE_STATUS_MASK … #define CXL_RAS_CORRECTABLE_MASK_OFFSET … #define CXL_RAS_CORRECTABLE_MASK_MASK … #define CXL_RAS_CAP_CONTROL_OFFSET … #define CXL_RAS_CAP_CONTROL_FE_MASK … #define CXL_RAS_HEADER_LOG_OFFSET … #define CXL_RAS_CAPABILITY_LENGTH … #define CXL_HEADERLOG_SIZE … #define CXL_HEADERLOG_SIZE_U32 … /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ #define CXLDEV_CAP_ARRAY_OFFSET … #define CXLDEV_CAP_ARRAY_CAP_ID … #define CXLDEV_CAP_ARRAY_ID_MASK … #define CXLDEV_CAP_ARRAY_COUNT_MASK … /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ #define CXLDEV_CAP_HDR_CAP_ID_MASK … /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS … #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX … #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX … #define CXLDEV_CAP_CAP_ID_MEMDEV … /* CXL 3.0 8.2.8.3.1 Event Status Register */ #define CXLDEV_DEV_EVENT_STATUS_OFFSET … #define CXLDEV_EVENT_STATUS_INFO … #define CXLDEV_EVENT_STATUS_WARN … #define CXLDEV_EVENT_STATUS_FAIL … #define CXLDEV_EVENT_STATUS_FATAL … #define CXLDEV_EVENT_STATUS_ALL … /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */ #define CXLDEV_EVENT_INT_MODE_MASK … #define CXLDEV_EVENT_INT_MSGNUM_MASK … /* CXL 2.0 8.2.8.4 Mailbox Registers */ #define CXLDEV_MBOX_CAPS_OFFSET … #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK … #define CXLDEV_MBOX_CAP_BG_CMD_IRQ … #define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK … #define CXLDEV_MBOX_CTRL_OFFSET … #define CXLDEV_MBOX_CTRL_DOORBELL … #define CXLDEV_MBOX_CTRL_BG_CMD_IRQ … #define CXLDEV_MBOX_CMD_OFFSET … #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK … #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK … #define CXLDEV_MBOX_STATUS_OFFSET … #define CXLDEV_MBOX_STATUS_BG_CMD … #define CXLDEV_MBOX_STATUS_RET_CODE_MASK … #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET … #define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK … #define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK … #define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK … #define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK … #define CXLDEV_MBOX_PAYLOAD_OFFSET … /* * Using struct_group() allows for per register-block-type helper routines, * without requiring block-type agnostic code to include the prefix. */ struct cxl_regs { … }; struct cxl_reg_map { … }; struct cxl_component_reg_map { … }; struct cxl_device_reg_map { … }; struct cxl_pmu_reg_map { … }; /** * struct cxl_register_map - DVSEC harvested register block mapping parameters * @host: device for devm operations and logging * @base: virtual base of the register-block-BAR + @block_offset * @resource: physical resource base of the register block * @max_size: maximum mapping size to perform register search * @reg_type: see enum cxl_regloc_type * @component_map: cxl_reg_map for component registers * @device_map: cxl_reg_maps for device registers * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units */ struct cxl_register_map { … }; void cxl_probe_component_regs(struct device *dev, void __iomem *base, struct cxl_component_reg_map *map); void cxl_probe_device_regs(struct device *dev, void __iomem *base, struct cxl_device_reg_map *map); int cxl_map_component_regs(const struct cxl_register_map *map, struct cxl_component_regs *regs, unsigned long map_mask); int cxl_map_device_regs(const struct cxl_register_map *map, struct cxl_device_regs *regs); int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs); enum cxl_regloc_type; int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type); int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map, int index); int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map); int cxl_setup_regs(struct cxl_register_map *map); struct cxl_dport; resource_size_t cxl_rcd_component_reg_phys(struct device *dev, struct cxl_dport *dport); #define CXL_RESOURCE_NONE … #define CXL_TARGET_STRLEN … /* * cxl_decoder flags that define the type of memory / devices this * decoder supports as well as configuration lock status See "CXL 2.0 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. * Additionally indicate whether decoder settings were autodetected, * user customized. */ #define CXL_DECODER_F_RAM … #define CXL_DECODER_F_PMEM … #define CXL_DECODER_F_TYPE2 … #define CXL_DECODER_F_TYPE3 … #define CXL_DECODER_F_LOCK … #define CXL_DECODER_F_ENABLE … #define CXL_DECODER_F_MASK … enum cxl_decoder_type { … }; /* * Current specification goes up to 8, double that seems a reasonable * software max for the foreseeable future */ #define CXL_DECODER_MAX_INTERLEAVE … #define CXL_QOS_CLASS_INVALID … /** * struct cxl_decoder - Common CXL HDM Decoder Attributes * @dev: this decoder's device * @id: kernel device name id * @hpa_range: Host physical address range mapped by this decoder * @interleave_ways: number of cxl_dports in this decode * @interleave_granularity: data stride per dport * @target_type: accelerator vs expander (type2 vs type3) selector * @region: currently assigned region for this decoder * @flags: memory type capabilities and locking * @commit: device/decoder-type specific callback to commit settings to hw * @reset: device/decoder-type specific callback to reset hw settings */ struct cxl_decoder { … }; /* * CXL_DECODER_DEAD prevents endpoints from being reattached to regions * while cxld_unregister() is running */ enum cxl_decoder_mode { … }; static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) { … } /* * Track whether this decoder is reserved for region autodiscovery, or * free for userspace provisioning. */ enum cxl_decoder_state { … }; /** * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder * @cxld: base cxl_decoder_object * @dpa_res: actively claimed DPA span of this decoder * @skip: offset into @dpa_res where @cxld.hpa_range maps * @mode: which memory type / access-mode-partition this decoder targets * @state: autodiscovery state * @pos: interleave position in @cxld.region */ struct cxl_endpoint_decoder { … }; /** * struct cxl_switch_decoder - Switch specific CXL HDM Decoder * @cxld: base cxl_decoder object * @nr_targets: number of elements in @target * @target: active ordered target list in current decoder configuration * * The 'switch' decoder type represents the decoder instances of cxl_port's that * route from the root of a CXL memory decode topology to the endpoints. They * come in two flavors, root-level decoders, statically defined by platform * firmware, and mid-level decoders, where interleave-granularity, * interleave-width, and the target list are mutable. */ struct cxl_switch_decoder { … }; struct cxl_root_decoder; cxl_hpa_to_spa_fn; /** * struct cxl_root_decoder - Static platform CXL address decoder * @res: host / parent resource for region allocations * @region_id: region id for next region provisioning event * @hpa_to_spa: translate CXL host-physical-address to Platform system-physical-address * @platform_data: platform specific configuration data * @range_lock: sync region autodiscovery by address range * @qos_class: QoS performance class cookie * @cxlsd: base cxl switch decoder */ struct cxl_root_decoder { … }; /* * enum cxl_config_state - State machine for region configuration * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more * changes to interleave_ways or interleave_granularity * @CXL_CONFIG_ACTIVE: All targets have been added the region is now * active * @CXL_CONFIG_RESET_PENDING: see commit_store() * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware */ enum cxl_config_state { … }; /** * struct cxl_region_params - region settings * @state: allow the driver to lockdown further parameter changes * @uuid: unique id for persistent regions * @interleave_ways: number of endpoints in the region * @interleave_granularity: capacity each endpoint contributes to a stripe * @res: allocated iomem capacity for this region * @targets: active ordered targets in current decoder configuration * @nr_targets: number of targets * * State transitions are protected by the cxl_region_rwsem */ struct cxl_region_params { … }; /* * Indicate whether this region has been assembled by autodetection or * userspace assembly. Prevent endpoint decoders outside of automatic * detection from being added to the region. */ #define CXL_REGION_F_AUTO … /* * Require that a committed region successfully complete a teardown once * any of its associated decoders have been torn down. This maintains * the commit state for the region since there are committed decoders, * but blocks cxl_region_probe(). */ #define CXL_REGION_F_NEEDS_RESET … /** * struct cxl_region - CXL region * @dev: This region's device * @id: This region's id. Id is globally unique across all regions * @mode: Endpoint decoder allocation / access mode * @type: Endpoint decoder target type * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge * @flags: Region state flags * @params: active + config params for the region * @coord: QoS access coordinates for the region * @memory_notifier: notifier for setting the access coordinates to node * @adist_notifier: notifier for calculating the abstract distance of node */ struct cxl_region { … }; struct cxl_nvdimm_bridge { … }; #define CXL_DEV_ID_LEN … struct cxl_nvdimm { … }; struct cxl_pmem_region_mapping { … }; struct cxl_pmem_region { … }; struct cxl_dax_region { … }; /** * struct cxl_port - logical collection of upstream port devices and * downstream port devices to construct a CXL memory * decode hierarchy. * @dev: this port's device * @uport_dev: PCI or platform device implementing the upstream port capability * @host_bridge: Shortcut to the platform attach point for this port * @id: id for port device-name * @dports: cxl_dport instances referenced by decoders * @endpoints: cxl_ep instances, endpoints that are a descendant of this port * @regions: cxl_region_ref instances, regions mapped by this port * @parent_dport: dport that points to this port in the parent * @decoder_ida: allocator for decoder ids * @reg_map: component and ras register mapping parameters * @nr_dports: number of entries in @dports * @hdm_end: track last allocated HDM decoder instance for allocation ordering * @commit_end: cursor to track highest committed decoder for commit ordering * @dead: last ep has been removed, force port re-creation * @depth: How deep this port is relative to the root. depth 0 is the root. * @cdat: Cached CDAT data * @cdat_available: Should a CDAT attribute be available in sysfs * @pci_latency: Upstream latency in picoseconds */ struct cxl_port { … }; /** * struct cxl_root - logical collection of root cxl_port items * * @port: cxl_port member * @ops: cxl root operations */ struct cxl_root { … }; static inline struct cxl_root * to_cxl_root(const struct cxl_port *port) { … } struct cxl_root_ops { … }; static inline struct cxl_dport * cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) { … } struct cxl_rcrb_info { … }; /** * struct cxl_dport - CXL downstream port * @dport_dev: PCI bridge or firmware device representing the downstream link * @reg_map: component and ras register mapping parameters * @port_id: unique hardware identifier for dport in decoder target list * @rcrb: Data about the Root Complex Register Block layout * @rch: Indicate whether this dport was enumerated in RCH or VH mode * @port: reference to cxl_port that contains this downstream port * @regs: Dport parsed register blocks * @coord: access coordinates (bandwidth and latency performance attributes) * @link_latency: calculated PCIe downstream latency */ struct cxl_dport { … }; /** * struct cxl_ep - track an endpoint's interest in a port * @ep: device that hosts a generic CXL endpoint (expander or accelerator) * @dport: which dport routes to this endpoint on @port * @next: cxl switch port across the link attached to @dport NULL if * attached to an endpoint */ struct cxl_ep { … }; /** * struct cxl_region_ref - track a region's interest in a port * @port: point in topology to install this reference * @decoder: decoder assigned for @region in @port * @region: region for this reference * @endpoints: cxl_ep references for region members beneath @port * @nr_targets_set: track how many targets have been programmed during setup * @nr_eps: number of endpoints beneath @port * @nr_targets: number of distinct targets needed to reach @nr_eps */ struct cxl_region_ref { … }; /* * The platform firmware device hosting the root is also the top of the * CXL port topology. All other CXL ports have another CXL port as their * parent and their ->uport_dev / host device is out-of-line of the port * ancestry. */ static inline bool is_cxl_root(struct cxl_port *port) { … } int cxl_num_decoders_committed(struct cxl_port *port); bool is_cxl_port(const struct device *dev); struct cxl_port *to_cxl_port(const struct device *dev); struct pci_bus; int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev, struct pci_bus *bus); struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport_dev, resource_size_t component_reg_phys, struct cxl_dport *parent_dport); struct cxl_root *devm_cxl_add_root(struct device *host, const struct cxl_root_ops *ops); struct cxl_root *find_cxl_root(struct cxl_port *port); void put_cxl_root(struct cxl_root *cxl_root); DEFINE_FREE(…) int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); void cxl_bus_rescan(void); void cxl_bus_drain(void); struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev, struct cxl_dport **dport); struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, struct cxl_dport **dport); bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, struct device *dport, int port_id, resource_size_t component_reg_phys); struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, struct device *dport_dev, int port_id, resource_size_t rcrb); #ifdef CONFIG_PCIEAER_CXL void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport); #else static inline void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport) { } #endif struct cxl_decoder *to_cxl_decoder(struct device *dev); struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); bool is_root_decoder(struct device *dev); bool is_switch_decoder(struct device *dev); bool is_endpoint_decoder(struct device *dev); struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, unsigned int nr_targets); struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, unsigned int nr_targets); int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); static inline int cxl_root_decoder_autoremove(struct device *host, struct cxl_root_decoder *cxlrd) { … } int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); /** * struct cxl_endpoint_dvsec_info - Cached DVSEC info * @mem_enabled: cached value of mem_enabled in the DVSEC at init time * @ranges: Number of active HDM ranges this device uses. * @port: endpoint port associated with this info instance * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE */ struct cxl_endpoint_dvsec_info { … }; struct cxl_hdm; struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, struct cxl_endpoint_dvsec_info *info); int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info); int devm_cxl_add_passthrough_decoder(struct cxl_port *port); int cxl_dvsec_rr_decode(struct device *dev, int dvsec, struct cxl_endpoint_dvsec_info *info); bool is_cxl_region(struct device *dev); extern struct bus_type cxl_bus_type; struct cxl_driver { … }; #define to_cxl_drv(__drv) … int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, const char *modname); #define cxl_driver_register(x) … void cxl_driver_unregister(struct cxl_driver *cxl_drv); #define module_cxl_driver(__cxl_driver) … #define CXL_DEVICE_NVDIMM_BRIDGE … #define CXL_DEVICE_NVDIMM … #define CXL_DEVICE_PORT … #define CXL_DEVICE_ROOT … #define CXL_DEVICE_MEMORY_EXPANDER … #define CXL_DEVICE_REGION … #define CXL_DEVICE_PMEM_REGION … #define CXL_DEVICE_DAX_REGION … #define CXL_DEVICE_PMU … #define MODULE_ALIAS_CXL(type) … #define CXL_MODALIAS_FMT … struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, struct cxl_port *port); struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); bool is_cxl_nvdimm(struct device *dev); bool is_cxl_nvdimm_bridge(struct device *dev); int devm_cxl_add_nvdimm(struct cxl_port *parent_port, struct cxl_memdev *cxlmd); struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port); #ifdef CONFIG_CXL_REGION bool is_cxl_pmem_region(struct device *dev); struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); int cxl_add_to_region(struct cxl_port *root, struct cxl_endpoint_decoder *cxled); struct cxl_dax_region *to_cxl_dax_region(struct device *dev); #else static inline bool is_cxl_pmem_region(struct device *dev) { return false; } static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) { return NULL; } static inline int cxl_add_to_region(struct cxl_port *root, struct cxl_endpoint_decoder *cxled) { return 0; } static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) { return NULL; } #endif void cxl_endpoint_parse_cdat(struct cxl_port *port); void cxl_switch_parse_cdat(struct cxl_port *port); int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, struct access_coordinate *coord); void cxl_region_perf_data_calculate(struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled); void cxl_memdev_update_perf(struct cxl_memdev *cxlmd); void cxl_coordinates_combine(struct access_coordinate *out, struct access_coordinate *c1, struct access_coordinate *c2); bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port); /* * Unit test builds overrides this to __weak, find the 'strong' version * of these symbols in tools/testing/cxl/. */ #ifndef __mock #define __mock … #endif #endif /* __CXL_H__ */
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