#ifndef __CXL_PCI_H__
#define __CXL_PCI_H__
#include <linux/pci.h>
#include "cxl.h"
#define CXL_MEMORY_PROGIF …
#define PCI_DVSEC_HEADER1_LENGTH_MASK …
#define CXL_DVSEC_PCIE_DEVICE …
#define CXL_DVSEC_CAP_OFFSET …
#define CXL_DVSEC_MEM_CAPABLE …
#define CXL_DVSEC_HDM_COUNT_MASK …
#define CXL_DVSEC_CTRL_OFFSET …
#define CXL_DVSEC_MEM_ENABLE …
#define CXL_DVSEC_RANGE_SIZE_HIGH(i) …
#define CXL_DVSEC_RANGE_SIZE_LOW(i) …
#define CXL_DVSEC_MEM_INFO_VALID …
#define CXL_DVSEC_MEM_ACTIVE …
#define CXL_DVSEC_MEM_SIZE_LOW_MASK …
#define CXL_DVSEC_RANGE_BASE_HIGH(i) …
#define CXL_DVSEC_RANGE_BASE_LOW(i) …
#define CXL_DVSEC_MEM_BASE_LOW_MASK …
#define CXL_DVSEC_RANGE_MAX …
#define CXL_DVSEC_FUNCTION_MAP …
#define CXL_DVSEC_PORT_EXTENSIONS …
#define CXL_DVSEC_PORT_GPF …
#define CXL_DVSEC_DEVICE_GPF …
#define CXL_DVSEC_PCIE_FLEXBUS_PORT …
#define CXL_DVSEC_REG_LOCATOR …
#define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET …
#define CXL_DVSEC_REG_LOCATOR_BIR_MASK …
#define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK …
#define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK …
#define CXL_PCI_DEFAULT_MAX_VECTORS …
enum cxl_regloc_type { … };
struct cdat_header { … } __packed;
struct cdat_entry_header { … } __packed;
cdat_data __packed;
struct cdat_doe_rsp { … } __packed;
static inline bool cxl_pci_flit_256(struct pci_dev *pdev)
{ … }
int devm_cxl_port_enumerate_dports(struct cxl_port *port);
struct cxl_dev_state;
int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
struct cxl_endpoint_dvsec_info *info);
void read_cdat_data(struct cxl_port *port);
void cxl_cor_error_detected(struct pci_dev *pdev);
pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
pci_channel_state_t state);
#endif