/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ /* QLogic qed NIC Driver * Copyright (c) 2015-2016 QLogic Corporation * Copyright (c) 2019-2021 Marvell International Ltd. */ #ifndef _COMMON_HSI_H #define _COMMON_HSI_H #include <linux/types.h> #include <asm/byteorder.h> #include <linux/bitops.h> #include <linux/slab.h> /* dma_addr_t manip */ #define PTR_LO(x) … #define PTR_HI(x) … #define DMA_LO_LE(x) … #define DMA_HI_LE(x) … #define DMA_REGPAIR_LE(x, val) … #define HILO_GEN(hi, lo, type) … #define HILO_64(hi, lo) … #define HILO_64_REGPAIR(regpair) … #define HILO_DMA_REGPAIR(regpair) … #ifndef __COMMON_HSI__ #define __COMMON_HSI__ /********************************/ /* PROTOCOL COMMON FW CONSTANTS */ /********************************/ #define X_FINAL_CLEANUP_AGG_INT … #define EVENT_RING_PAGE_SIZE_BYTES … #define NUM_OF_GLOBAL_QUEUES … #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE … #define ISCSI_CDU_TASK_SEG_TYPE … #define FCOE_CDU_TASK_SEG_TYPE … #define RDMA_CDU_TASK_SEG_TYPE … #define ETH_CDU_TASK_SEG_TYPE … #define FW_ASSERT_GENERAL_ATTN_IDX … /* Queue Zone sizes in bytes */ #define TSTORM_QZONE_SIZE … #define MSTORM_QZONE_SIZE … #define USTORM_QZONE_SIZE … #define XSTORM_QZONE_SIZE … #define YSTORM_QZONE_SIZE … #define PSTORM_QZONE_SIZE … #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG … #define ETH_MAX_RXQ_VF_DEFAULT … #define ETH_MAX_RXQ_VF_DOUBLE … #define ETH_MAX_RXQ_VF_QUAD … #define ETH_RGSRC_CTX_SIZE … #define ETH_TGSRC_CTX_SIZE … /********************************/ /* CORE (LIGHT L2) FW CONSTANTS */ /********************************/ #define CORE_LL2_MAX_RAMROD_PER_CON … #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES … #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES … #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES … #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS … #define CORE_LL2_TX_MAX_BDS_PER_PACKET … #define CORE_SPQE_PAGE_SIZE_BYTES … /* Number of LL2 RAM based queues */ #define MAX_NUM_LL2_RX_RAM_QUEUES … /* Number of LL2 context based queues */ #define MAX_NUM_LL2_RX_CTX_QUEUES … #define MAX_NUM_LL2_RX_QUEUES … #define MAX_NUM_LL2_TX_STATS_COUNTERS … #define FW_MAJOR_VERSION … #define FW_MINOR_VERSION … #define FW_REVISION_VERSION … #define FW_ENGINEERING_VERSION … /***********************/ /* COMMON HW CONSTANTS */ /***********************/ /* PCI functions */ #define MAX_NUM_PORTS_K2 … #define MAX_NUM_PORTS_BB … #define MAX_NUM_PORTS … #define MAX_NUM_PFS_K2 … #define MAX_NUM_PFS_BB … #define MAX_NUM_PFS … #define MAX_NUM_OF_PFS_IN_CHIP … #define MAX_NUM_VFS_K2 … #define MAX_NUM_VFS_BB … #define MAX_NUM_VFS … #define MAX_NUM_FUNCTIONS_BB … #define MAX_NUM_FUNCTIONS_K2 … #define MAX_FUNCTION_NUMBER_BB … #define MAX_FUNCTION_NUMBER_K2 … #define MAX_NUM_FUNCTIONS … #define MAX_NUM_VPORTS_K2 … #define MAX_NUM_VPORTS_BB … #define MAX_NUM_VPORTS … #define MAX_NUM_L2_QUEUES_K2 … #define MAX_NUM_L2_QUEUES_BB … #define MAX_NUM_L2_QUEUES … /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ #define NUM_PHYS_TCS_4PORT_K2 … #define NUM_OF_PHYS_TCS … #define PURE_LB_TC … #define NUM_TCS_4PORT_K2 … #define NUM_OF_TCS … /* CIDs */ #define NUM_OF_CONNECTION_TYPES … #define NUM_OF_LCIDS … #define NUM_OF_LTIDS … /* Global PXP windows (GTT) */ #define NUM_OF_GTT … #define GTT_DWORD_SIZE_BITS … #define GTT_BYTE_SIZE_BITS … #define GTT_DWORD_SIZE … /* Tools Version */ #define TOOLS_VERSION … /*****************/ /* CDU CONSTANTS */ /*****************/ #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT … #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK … #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT … #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK … #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT … #define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT … #define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE … #define CDU_CONTEXT_VALIDATION_CFG_USE_REGION … #define CDU_CONTEXT_VALIDATION_CFG_USE_CID … #define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE … #define CDU_CONTEXT_VALIDATION_DEFAULT_CFG … /*****************/ /* DQ CONSTANTS */ /*****************/ /* DEMS */ #define DQ_DEMS_LEGACY … #define DQ_DEMS_TOE_MORE_TO_SEND … #define DQ_DEMS_TOE_LOCAL_ADV_WND … #define DQ_DEMS_ROCE_CQ_CONS … /* XCM agg val selection (HW) */ #define DQ_XCM_AGG_VAL_SEL_WORD2 … #define DQ_XCM_AGG_VAL_SEL_WORD3 … #define DQ_XCM_AGG_VAL_SEL_WORD4 … #define DQ_XCM_AGG_VAL_SEL_WORD5 … #define DQ_XCM_AGG_VAL_SEL_REG3 … #define DQ_XCM_AGG_VAL_SEL_REG4 … #define DQ_XCM_AGG_VAL_SEL_REG5 … #define DQ_XCM_AGG_VAL_SEL_REG6 … /* XCM agg val selection (FW) */ #define DQ_XCM_CORE_TX_BD_CONS_CMD … #define DQ_XCM_CORE_TX_BD_PROD_CMD … #define DQ_XCM_CORE_SPQ_PROD_CMD … #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD … #define DQ_XCM_ETH_TX_BD_CONS_CMD … #define DQ_XCM_ETH_TX_BD_PROD_CMD … #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD … #define DQ_XCM_FCOE_SQ_CONS_CMD … #define DQ_XCM_FCOE_SQ_PROD_CMD … #define DQ_XCM_FCOE_X_FERQ_PROD_CMD … #define DQ_XCM_ISCSI_SQ_CONS_CMD … #define DQ_XCM_ISCSI_SQ_PROD_CMD … #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD … #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD … #define DQ_XCM_ROCE_SQ_PROD_CMD … #define DQ_XCM_TOE_TX_BD_PROD_CMD … #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD … #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD … #define DQ_XCM_ROCE_ACK_EDPM_DORQ_SEQ_CMD … /* UCM agg val selection (HW) */ #define DQ_UCM_AGG_VAL_SEL_WORD0 … #define DQ_UCM_AGG_VAL_SEL_WORD1 … #define DQ_UCM_AGG_VAL_SEL_WORD2 … #define DQ_UCM_AGG_VAL_SEL_WORD3 … #define DQ_UCM_AGG_VAL_SEL_REG0 … #define DQ_UCM_AGG_VAL_SEL_REG1 … #define DQ_UCM_AGG_VAL_SEL_REG2 … #define DQ_UCM_AGG_VAL_SEL_REG3 … /* UCM agg val selection (FW) */ #define DQ_UCM_ETH_PMD_TX_CONS_CMD … #define DQ_UCM_ETH_PMD_RX_CONS_CMD … #define DQ_UCM_ROCE_CQ_CONS_CMD … #define DQ_UCM_ROCE_CQ_PROD_CMD … /* TCM agg val selection (HW) */ #define DQ_TCM_AGG_VAL_SEL_WORD0 … #define DQ_TCM_AGG_VAL_SEL_WORD1 … #define DQ_TCM_AGG_VAL_SEL_WORD2 … #define DQ_TCM_AGG_VAL_SEL_WORD3 … #define DQ_TCM_AGG_VAL_SEL_REG1 … #define DQ_TCM_AGG_VAL_SEL_REG2 … #define DQ_TCM_AGG_VAL_SEL_REG6 … #define DQ_TCM_AGG_VAL_SEL_REG9 … /* TCM agg val selection (FW) */ #define DQ_TCM_L2B_BD_PROD_CMD … #define DQ_TCM_ROCE_RQ_PROD_CMD … /* XCM agg counter flag selection (HW) */ #define DQ_XCM_AGG_FLG_SHIFT_BIT14 … #define DQ_XCM_AGG_FLG_SHIFT_BIT15 … #define DQ_XCM_AGG_FLG_SHIFT_CF12 … #define DQ_XCM_AGG_FLG_SHIFT_CF13 … #define DQ_XCM_AGG_FLG_SHIFT_CF18 … #define DQ_XCM_AGG_FLG_SHIFT_CF19 … #define DQ_XCM_AGG_FLG_SHIFT_CF22 … #define DQ_XCM_AGG_FLG_SHIFT_CF23 … /* XCM agg counter flag selection (FW) */ #define DQ_XCM_CORE_DQ_CF_CMD … #define DQ_XCM_CORE_TERMINATE_CMD … #define DQ_XCM_CORE_SLOW_PATH_CMD … #define DQ_XCM_ETH_DQ_CF_CMD … #define DQ_XCM_ETH_TERMINATE_CMD … #define DQ_XCM_ETH_SLOW_PATH_CMD … #define DQ_XCM_ETH_TPH_EN_CMD … #define DQ_XCM_FCOE_SLOW_PATH_CMD … #define DQ_XCM_ISCSI_DQ_FLUSH_CMD … #define DQ_XCM_ISCSI_SLOW_PATH_CMD … #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD … #define DQ_XCM_TOE_DQ_FLUSH_CMD … #define DQ_XCM_TOE_SLOW_PATH_CMD … /* UCM agg counter flag selection (HW) */ #define DQ_UCM_AGG_FLG_SHIFT_CF0 … #define DQ_UCM_AGG_FLG_SHIFT_CF1 … #define DQ_UCM_AGG_FLG_SHIFT_CF3 … #define DQ_UCM_AGG_FLG_SHIFT_CF4 … #define DQ_UCM_AGG_FLG_SHIFT_CF5 … #define DQ_UCM_AGG_FLG_SHIFT_CF6 … #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN … #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN … /* UCM agg counter flag selection (FW) */ #define DQ_UCM_ETH_PMD_TX_ARM_CMD … #define DQ_UCM_ETH_PMD_RX_ARM_CMD … #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD … #define DQ_UCM_ROCE_CQ_ARM_CF_CMD … #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD … #define DQ_UCM_TOE_SLOW_PATH_CF_CMD … #define DQ_UCM_TOE_DQ_CF_CMD … /* TCM agg counter flag selection (HW) */ #define DQ_TCM_AGG_FLG_SHIFT_CF0 … #define DQ_TCM_AGG_FLG_SHIFT_CF1 … #define DQ_TCM_AGG_FLG_SHIFT_CF2 … #define DQ_TCM_AGG_FLG_SHIFT_CF3 … #define DQ_TCM_AGG_FLG_SHIFT_CF4 … #define DQ_TCM_AGG_FLG_SHIFT_CF5 … #define DQ_TCM_AGG_FLG_SHIFT_CF6 … #define DQ_TCM_AGG_FLG_SHIFT_CF7 … /* TCM agg counter flag selection (FW) */ #define DQ_TCM_FCOE_FLUSH_Q0_CMD … #define DQ_TCM_FCOE_DUMMY_TIMER_CMD … #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD … #define DQ_TCM_ISCSI_FLUSH_Q0_CMD … #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD … #define DQ_TCM_TOE_FLUSH_Q0_CMD … #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD … #define DQ_TCM_IWARP_POST_RQ_CF_CMD … /* PWM address mapping */ #define DQ_PWM_OFFSET_DPM_BASE … #define DQ_PWM_OFFSET_DPM_END … #define DQ_PWM_OFFSET_XCM32_24ICID_BASE … #define DQ_PWM_OFFSET_UCM32_24ICID_BASE … #define DQ_PWM_OFFSET_TCM32_24ICID_BASE … #define DQ_PWM_OFFSET_XCM16_BASE … #define DQ_PWM_OFFSET_XCM32_BASE … #define DQ_PWM_OFFSET_UCM16_BASE … #define DQ_PWM_OFFSET_UCM32_BASE … #define DQ_PWM_OFFSET_UCM16_4 … #define DQ_PWM_OFFSET_TCM16_BASE … #define DQ_PWM_OFFSET_TCM32_BASE … #define DQ_PWM_OFFSET_XCM_FLAGS … #define DQ_PWM_OFFSET_UCM_FLAGS … #define DQ_PWM_OFFSET_TCM_FLAGS … #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD … #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT … #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT … #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT … #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS … #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD … #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD … /* DQ_DEMS_AGG_VAL_BASE */ #define DQ_PWM_OFFSET_TCM_LL2_PROD_UPDATE … #define DQ_PWM_OFFSET_XCM_RDMA_24B_ICID_SQ_PROD … #define DQ_PWM_OFFSET_UCM_RDMA_24B_ICID_CQ_CONS_32BIT … #define DQ_PWM_OFFSET_TCM_ROCE_24B_ICID_RQ_PROD … #define DQ_REGION_SHIFT … /* DPM */ #define DQ_DPM_WQE_BUFF_SIZE … /* Conn type ranges */ #define DQ_CONN_TYPE_RANGE_SHIFT … /*****************/ /* QM CONSTANTS */ /*****************/ /* Number of TX queues in the QM */ #define MAX_QM_TX_QUEUES_K2 … #define MAX_QM_TX_QUEUES_BB … #define MAX_QM_TX_QUEUES … /* Number of Other queues in the QM */ #define MAX_QM_OTHER_QUEUES_BB … #define MAX_QM_OTHER_QUEUES_K2 … #define MAX_QM_OTHER_QUEUES … /* Number of queues in a PF queue group */ #define QM_PF_QUEUE_GROUP_SIZE … /* The size of a single queue element in bytes */ #define QM_PQ_ELEMENT_SIZE … /* Base number of Tx PQs in the CM PQ representation. * Should be used when storing PQ IDs in CM PQ registers and context. */ #define CM_TX_PQ_BASE … /* Number of global Vport/QCN rate limiters */ #define MAX_QM_GLOBAL_RLS … #define COMMON_MAX_QM_GLOBAL_RLS … /* QM registers data */ #define QM_LINE_CRD_REG_WIDTH … #define QM_LINE_CRD_REG_SIGN_BIT … #define QM_BYTE_CRD_REG_WIDTH … #define QM_BYTE_CRD_REG_SIGN_BIT … #define QM_WFQ_CRD_REG_WIDTH … #define QM_WFQ_CRD_REG_SIGN_BIT … #define QM_RL_CRD_REG_WIDTH … #define QM_RL_CRD_REG_SIGN_BIT … /*****************/ /* CAU CONSTANTS */ /*****************/ #define CAU_FSM_ETH_RX … #define CAU_FSM_ETH_TX … /* Number of Protocol Indices per Status Block */ #define PIS_PER_SB … #define MAX_PIS_PER_SB … #define CAU_HC_STOPPED_STATE … #define CAU_HC_DISABLE_STATE … #define CAU_HC_ENABLE_STATE … /*****************/ /* IGU CONSTANTS */ /*****************/ #define MAX_SB_PER_PATH_K2 … #define MAX_SB_PER_PATH_BB … #define MAX_TOT_SB_PER_PATH … #define MAX_SB_PER_PF_MIMD … #define MAX_SB_PER_PF_SIMD … #define MAX_SB_PER_VF … /* Memory addresses on the BAR for the IGU Sub Block */ #define IGU_MEM_BASE … #define IGU_MEM_MSIX_BASE … #define IGU_MEM_MSIX_UPPER … #define IGU_MEM_MSIX_RESERVED_UPPER … #define IGU_MEM_PBA_MSIX_BASE … #define IGU_MEM_PBA_MSIX_UPPER … #define IGU_MEM_PBA_MSIX_RESERVED_UPPER … #define IGU_CMD_INT_ACK_BASE … #define IGU_CMD_INT_ACK_RESERVED_UPPER … #define IGU_CMD_ATTN_BIT_UPD_UPPER … #define IGU_CMD_ATTN_BIT_SET_UPPER … #define IGU_CMD_ATTN_BIT_CLR_UPPER … #define IGU_REG_SISR_MDPC_WMASK_UPPER … #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER … #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER … #define IGU_REG_SISR_MDPC_WOMASK_UPPER … #define IGU_CMD_PROD_UPD_BASE … #define IGU_CMD_PROD_UPD_RESERVED_UPPER … /*****************/ /* PXP CONSTANTS */ /*****************/ /* Bars for Blocks */ #define PXP_BAR_GRC … #define PXP_BAR_TSDM … #define PXP_BAR_USDM … #define PXP_BAR_XSDM … #define PXP_BAR_MSDM … #define PXP_BAR_YSDM … #define PXP_BAR_PSDM … #define PXP_BAR_IGU … #define PXP_BAR_DQ … /* PTT and GTT */ #define PXP_PER_PF_ENTRY_SIZE … #define PXP_NUM_GLOBAL_WINDOWS … #define PXP_GLOBAL_ENTRY_SIZE … #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH … #define PXP_PF_WINDOW_ADMIN_START … #define PXP_PF_WINDOW_ADMIN_LENGTH … #define PXP_PF_WINDOW_ADMIN_END … #define PXP_PF_WINDOW_ADMIN_PER_PF_START … #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH … #define PXP_PF_WINDOW_ADMIN_PER_PF_END … #define PXP_PF_WINDOW_ADMIN_GLOBAL_START … #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH … #define PXP_PF_WINDOW_ADMIN_GLOBAL_END … #define PXP_PF_GLOBAL_PRETEND_ADDR … #define PXP_PF_ME_OPAQUE_MASK_ADDR … #define PXP_PF_ME_OPAQUE_ADDR … #define PXP_PF_ME_CONCRETE_ADDR … #define PXP_NUM_PF_WINDOWS … #define PXP_EXTERNAL_BAR_PF_WINDOW_START … #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM … #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE … #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH … #define PXP_EXTERNAL_BAR_PF_WINDOW_END … #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START … #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM … #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE … #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH … #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END … /* PF BAR */ #define PXP_BAR0_START_GRC … #define PXP_BAR0_GRC_LENGTH … #define PXP_BAR0_END_GRC … #define PXP_BAR0_START_IGU … #define PXP_BAR0_IGU_LENGTH … #define PXP_BAR0_END_IGU … #define PXP_BAR0_START_TSDM … #define PXP_BAR0_SDM_LENGTH … #define PXP_BAR0_SDM_RESERVED_LENGTH … #define PXP_BAR0_END_TSDM … #define PXP_BAR0_START_MSDM … #define PXP_BAR0_END_MSDM … #define PXP_BAR0_START_USDM … #define PXP_BAR0_END_USDM … #define PXP_BAR0_START_XSDM … #define PXP_BAR0_END_XSDM … #define PXP_BAR0_START_YSDM … #define PXP_BAR0_END_YSDM … #define PXP_BAR0_START_PSDM … #define PXP_BAR0_END_PSDM … #define PXP_BAR0_FIRST_INVALID_ADDRESS … /* VF BAR */ #define PXP_VF_BAR0 … #define PXP_VF_BAR0_START_IGU … #define PXP_VF_BAR0_IGU_LENGTH … #define PXP_VF_BAR0_END_IGU … #define PXP_VF_BAR0_START_DQ … #define PXP_VF_BAR0_DQ_LENGTH … #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET … #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS … #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS … #define PXP_VF_BAR0_END_DQ … #define PXP_VF_BAR0_START_TSDM_ZONE_B … #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B … #define PXP_VF_BAR0_END_TSDM_ZONE_B … #define PXP_VF_BAR0_START_MSDM_ZONE_B … #define PXP_VF_BAR0_END_MSDM_ZONE_B … #define PXP_VF_BAR0_START_USDM_ZONE_B … #define PXP_VF_BAR0_END_USDM_ZONE_B … #define PXP_VF_BAR0_START_XSDM_ZONE_B … #define PXP_VF_BAR0_END_XSDM_ZONE_B … #define PXP_VF_BAR0_START_YSDM_ZONE_B … #define PXP_VF_BAR0_END_YSDM_ZONE_B … #define PXP_VF_BAR0_START_PSDM_ZONE_B … #define PXP_VF_BAR0_END_PSDM_ZONE_B … #define PXP_VF_BAR0_START_GRC … #define PXP_VF_BAR0_GRC_LENGTH … #define PXP_VF_BAR0_END_GRC … #define PXP_VF_BAR0_START_SDM_ZONE_A … #define PXP_VF_BAR0_END_SDM_ZONE_A … #define PXP_VF_BAR0_START_IGU2 … #define PXP_VF_BAR0_IGU2_LENGTH … #define PXP_VF_BAR0_END_IGU2 … #define PXP_VF_BAR0_GRC_WINDOW_LENGTH … #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN … #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER … /* ILT Records */ #define PXP_NUM_ILT_RECORDS_BB … #define PXP_NUM_ILT_RECORDS_K2 … #define MAX_NUM_ILT_RECORDS … /* Host Interface */ #define PXP_QUEUES_ZONE_MAX_NUM … /*****************/ /* PRM CONSTANTS */ /*****************/ #define PRM_DMA_PAD_BYTES_NUM … /*****************/ /* SDMs CONSTANTS */ /*****************/ #define SDM_OP_GEN_TRIG_NONE … #define SDM_OP_GEN_TRIG_WAKE_THREAD … #define SDM_OP_GEN_TRIG_AGG_INT … #define SDM_OP_GEN_TRIG_LOADER … #define SDM_OP_GEN_TRIG_INDICATE_ERROR … #define SDM_OP_GEN_TRIG_INC_ORDER_CNT … /********************/ /* Completion types */ /********************/ #define SDM_COMP_TYPE_NONE … #define SDM_COMP_TYPE_WAKE_THREAD … #define SDM_COMP_TYPE_AGG_INT … #define SDM_COMP_TYPE_CM … #define SDM_COMP_TYPE_LOADER … #define SDM_COMP_TYPE_PXP … #define SDM_COMP_TYPE_INDICATE_ERROR … #define SDM_COMP_TYPE_RELEASE_THREAD … #define SDM_COMP_TYPE_RAM … #define SDM_COMP_TYPE_INC_ORDER_CNT … /*****************/ /* PBF CONSTANTS */ /*****************/ /* Number of PBF command queue lines. Each line is 32B. */ #define PBF_MAX_CMD_LINES … /* Number of BTB blocks. Each block is 256B. */ #define BTB_MAX_BLOCKS_BB … #define BTB_MAX_BLOCKS_K2 … /*****************/ /* PRS CONSTANTS */ /*****************/ #define PRS_GFT_CAM_LINES_NO_MATCH … /* Interrupt coalescing TimeSet */ struct coalescing_timeset { … }; struct common_queue_zone { … }; /* ETH Rx producers data */ struct eth_rx_prod_data { … }; struct tcp_ulp_connect_done_params { … }; struct iscsi_connect_done_results { … }; struct iscsi_eqe_data { … }; /* Multi function mode */ enum mf_mode { … }; /* Per protocol packet duplication enable bit vector. If set, duplicate * offloaded traffic to LL2 debug queueu. */ struct offload_pkt_dup_enable { … }; /* Per-protocol connection types */ enum protocol_type { … }; /* Pstorm packet duplication config */ struct pstorm_pkt_dup_cfg { … }; struct regpair { … }; /* RoCE Destroy Event Data */ struct rdma_eqe_destroy_qp { … }; /* RoCE Suspend Event Data */ struct rdma_eqe_suspend_qp { … }; /* RDMA Event Data Union */ rdma_eqe_data; /* Tstorm packet duplication config */ struct tstorm_pkt_dup_cfg { … }; struct tstorm_queue_zone { … }; /* Ustorm Queue Zone */ struct ustorm_eth_queue_zone { … }; struct ustorm_queue_zone { … }; /* Status block structure */ struct cau_pi_entry { … }; /* Status block structure */ struct cau_sb_entry { … }; /* Igu cleanup bit values to distinguish between clean or producer consumer * update. */ enum command_type_bit { … }; /* Core doorbell data */ struct core_db_data { … }; /* Enum of doorbell aggregative command selection */ enum db_agg_cmd_sel { … }; /* Enum of doorbell destination */ enum db_dest { … }; /* Enum of doorbell DPM types */ enum db_dpm_type { … }; /* Structure for doorbell data, in L2 DPM mode, for 1st db in a DPM burst */ struct db_l2_dpm_data { … }; /* Structure for SGE in a DPM doorbell of type DPM_L2_BD */ struct db_l2_dpm_sge { … }; /* Structure for doorbell address, in legacy mode */ struct db_legacy_addr { … }; /* Structure for doorbell address, in legacy mode, without DEMS */ struct db_legacy_wo_dems_addr { … }; /* Structure for doorbell address, in PWM mode */ struct db_pwm_addr { … }; /* Parameters to RDMA firmware, passed in EDPM doorbell */ struct db_rdma_24b_icid_dpm_params { … }; /* Parameters to RDMA firmware, passed in EDPM doorbell */ struct db_rdma_dpm_params { … }; /* Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a * DPM burst. */ struct db_rdma_dpm_data { … }; /* Igu interrupt command */ enum igu_int_cmd { … }; /* IGU producer or consumer update command */ struct igu_prod_cons_update { … }; /* Igu segments access for default status block only */ enum igu_seg_access { … }; /* Enumeration for L3 type field of parsing_and_err_flags. * L3Type: 0 - unknown (not ip), 1 - Ipv4, 2 - Ipv6 * (This field can be filled according to the last-ethertype) */ enum l3_type { … }; /* Enumeration for l4Protocol field of parsing_and_err_flags. * L4-protocol: 0 - none, 1 - TCP, 2 - UDP. * If the packet is IPv4 fragment, and its not the first fragment, the * protocol-type should be set to none. */ enum l4_protocol { … }; /* Parsing and error flags field */ struct parsing_and_err_flags { … }; /* Parsing error flags bitmap */ struct parsing_err_flags { … }; /* Pb context */ struct pb_context { … }; /* Concrete Function ID */ struct pxp_concrete_fid { … }; /* Concrete Function ID */ struct pxp_pretend_concrete_fid { … }; /* Function ID */ pxp_pretend_fid; /* Pxp Pretend Command Register */ struct pxp_pretend_cmd { … }; /* PTT Record in PXP Admin Window */ struct pxp_ptt_entry { … }; /* VF Zone A Permission Register */ struct pxp_vf_zone_a_permission { … }; /* Rdif context */ struct rdif_task_context { … }; /* Searcher Table struct */ struct src_entry_header { … }; /* Enumeration for address type */ enum src_header_next_ptr_type_enum { … }; /* Status block structure */ struct status_block { … }; /* Tdif context */ struct tdif_task_context { … }; /* Timers context */ struct timers_context { … }; /* Enum for next_protocol field of tunnel_parsing_flags / tunnelTypeDesc */ enum tunnel_next_protocol { … }; #endif /* __COMMON_HSI__ */ #endif
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