/* SPDX-License-Identifier: GPL-2.0-only */ /* * QLogic Fibre Channel HBA Driver * Copyright (c) 2003-2014 QLogic Corporation */ #ifndef __QLA_NX2_H #define __QLA_NX2_H #define QSNT_ACK_TOV … #define INTENT_TO_RECOVER … #define PROCEED_TO_RECOVER … #define IDC_LOCK_RECOVERY_OWNER_MASK … #define IDC_LOCK_RECOVERY_STATE_MASK … #define IDC_LOCK_RECOVERY_STATE_SHIFT_BITS … #define QLA8044_DRV_LOCK_MSLEEP … #define QLA8044_ADDR_DDR_NET … #define QLA8044_ADDR_DDR_NET_MAX … #define MD_MIU_TEST_AGT_WRDATA_LO … #define MD_MIU_TEST_AGT_WRDATA_HI … #define MD_MIU_TEST_AGT_WRDATA_ULO … #define MD_MIU_TEST_AGT_WRDATA_UHI … /* MIU_TEST_AGT_CTRL flags. work for SIU as well */ #define MIU_TA_CTL_WRITE_ENABLE … #define MIU_TA_CTL_WRITE_START … #define MIU_TA_CTL_START_ENABLE … /* Imbus address bit used to indicate a host address. This bit is * eliminated by the pcie bar and bar select before presentation * over pcie. */ /* host memory via IMBUS */ #define QLA8044_P2_ADDR_PCIE … #define QLA8044_P3_ADDR_PCIE … #define QLA8044_ADDR_PCIE_MAX … #define QLA8044_ADDR_OCM0 … #define QLA8044_ADDR_OCM0_MAX … #define QLA8044_ADDR_OCM1 … #define QLA8044_ADDR_OCM1_MAX … #define QLA8044_ADDR_QDR_NET … #define QLA8044_P2_ADDR_QDR_NET_MAX … #define QLA8044_P3_ADDR_QDR_NET_MAX … #define QLA8044_ADDR_QDR_NET_MAX … #define QLA8044_PCI_CRBSPACE … #define QLA8044_PCI_DIRECT_CRB … #define QLA8044_PCI_CAMQM … #define QLA8044_PCI_CAMQM_MAX … #define QLA8044_PCI_DDR_NET … #define QLA8044_PCI_QDR_NET … #define QLA8044_PCI_QDR_NET_MAX … /* PCI Windowing for DDR regions. */ static inline bool addr_in_range(u64 addr, u64 low, u64 high) { … } /* Indirectly Mapped Registers */ #define QLA8044_FLASH_SPI_STATUS … #define QLA8044_FLASH_SPI_CONTROL … #define QLA8044_FLASH_STATUS … #define QLA8044_FLASH_CONTROL … #define QLA8044_FLASH_ADDR … #define QLA8044_FLASH_WRDATA … #define QLA8044_FLASH_RDDATA … #define QLA8044_FLASH_DIRECT_WINDOW … #define QLA8044_FLASH_DIRECT_DATA(DATA) … /* Flash access regs */ #define QLA8044_FLASH_LOCK … #define QLA8044_FLASH_UNLOCK … #define QLA8044_FLASH_LOCK_ID … /* Driver Lock regs */ #define QLA8044_DRV_LOCK … #define QLA8044_DRV_UNLOCK … #define QLA8044_DRV_LOCK_ID … #define QLA8044_DRV_LOCKRECOVERY … /* IDC version */ #define QLA8044_IDC_VER_MAJ_VALUE … #define QLA8044_IDC_VER_MIN_VALUE … /* IDC Registers : Driver Coexistence Defines */ #define QLA8044_CRB_IDC_VER_MAJOR … #define QLA8044_CRB_IDC_VER_MINOR … #define QLA8044_IDC_DRV_AUDIT … #define QLA8044_SRE_SHIM_CONTROL … #define QLA8044_PORT0_RXB_PAUSE_THRS … #define QLA8044_PORT1_RXB_PAUSE_THRS … #define QLA8044_PORT0_RXB_TC_MAX_CELL … #define QLA8044_PORT1_RXB_TC_MAX_CELL … #define QLA8044_PORT0_RXB_TC_STATS … #define QLA8044_PORT1_RXB_TC_STATS … #define QLA8044_PORT2_IFB_PAUSE_THRS … #define QLA8044_PORT3_IFB_PAUSE_THRS … /* set value to pause threshold value */ #define QLA8044_SET_PAUSE_VAL … #define QLA8044_SET_TC_MAX_CELL_VAL … #define QLA8044_PEG_HALT_STATUS1 … #define QLA8044_PEG_HALT_STATUS2 … #define QLA8044_PEG_ALIVE_COUNTER … #define QLA8044_FW_CAPABILITIES … #define QLA8044_CRB_DRV_ACTIVE … #define QLA8044_CRB_DEV_STATE … #define QLA8044_CRB_DRV_STATE … #define QLA8044_CRB_DRV_SCRATCH … #define QLA8044_CRB_DEV_PART_INFO1 … #define QLA8044_CRB_DEV_PART_INFO2 … #define QLA8044_FW_VER_MAJOR … #define QLA8044_FW_VER_MINOR … #define QLA8044_FW_VER_SUB … #define QLA8044_NPAR_STATE … #define QLA8044_FW_IMAGE_VALID … #define QLA8044_CMDPEG_STATE … #define QLA8044_ASIC_TEMP … #define QLA8044_FW_API … #define QLA8044_DRV_OP_MODE … #define QLA8044_CRB_WIN_BASE … #define QLA8044_CRB_WIN_FUNC(f) … #define QLA8044_SEM_LOCK_BASE … #define QLA8044_SEM_UNLOCK_BASE … #define QLA8044_SEM_LOCK_FUNC(f) … #define QLA8044_SEM_UNLOCK_FUNC(f) … #define QLA8044_LINK_STATE(f) … #define QLA8044_LINK_SPEED(f) … #define QLA8044_MAX_LINK_SPEED(f) … #define QLA8044_LINK_SPEED_FACTOR … #define QLA8044_FUN7_ACTIVE_INDEX … /* FLASH API Defines */ #define QLA8044_FLASH_MAX_WAIT_USEC … #define QLA8044_FLASH_LOCK_TIMEOUT … #define QLA8044_FLASH_SECTOR_SIZE … #define QLA8044_DRV_LOCK_TIMEOUT … #define QLA8044_FLASH_SECTOR_ERASE_CMD … #define QLA8044_FLASH_WRITE_CMD … #define QLA8044_FLASH_BUFFER_WRITE_CMD … #define QLA8044_FLASH_READ_RETRY_COUNT … #define QLA8044_FLASH_STATUS_READY … #define QLA8044_FLASH_BUFFER_WRITE_MIN … #define QLA8044_FLASH_BUFFER_WRITE_MAX … #define QLA8044_FLASH_STATUS_REG_POLL_DELAY … #define QLA8044_ERASE_MODE … #define QLA8044_WRITE_MODE … #define QLA8044_DWORD_WRITE_MODE … #define QLA8044_GLOBAL_RESET … #define QLA8044_WILDCARD … #define QLA8044_INFORMANT … #define QLA8044_HOST_MBX_CTRL … #define QLA8044_FW_MBX_CTRL … #define QLA8044_BOOTLOADER_ADDR … #define QLA8044_BOOTLOADER_SIZE … #define QLA8044_FW_IMAGE_ADDR … #define QLA8044_MBX_INTR_ENABLE … #define QLA8044_MBX_INTR_MASK … /* IDC Control Register bit defines */ #define DONTRESET_BIT0 … #define GRACEFUL_RESET_BIT1 … /* ISP8044 PEG_HALT_STATUS1 bits */ #define QLA8044_HALT_STATUS_INFORMATIONAL … #define QLA8044_HALT_STATUS_FW_RESET … #define QLA8044_HALT_STATUS_UNRECOVERABLE … /* Firmware image definitions */ #define QLA8044_BOOTLOADER_FLASH_ADDR … #define QLA8044_BOOT_FROM_FLASH … #define QLA8044_IDC_PARAM_ADDR … /* FLASH related definitions */ #define QLA8044_OPTROM_BURST_SIZE … #define QLA8044_MAX_OPTROM_BURST_DWORDS … #define QLA8044_MIN_OPTROM_BURST_DWORDS … #define QLA8044_SECTOR_SIZE … #define QLA8044_FLASH_SPI_CTL … #define QLA8044_FLASH_FIRST_TEMP_VAL … #define QLA8044_FLASH_SECOND_TEMP_VAL … #define QLA8044_FLASH_FIRST_MS_PATTERN … #define QLA8044_FLASH_SECOND_MS_PATTERN … #define QLA8044_FLASH_LAST_MS_PATTERN … #define QLA8044_FLASH_STATUS_WRITE_DEF_SIG … #define QLA8044_FLASH_SECOND_ERASE_MS_VAL … #define QLA8044_FLASH_ERASE_SIG … #define QLA8044_FLASH_LAST_ERASE_MS_VAL … /* Reset template definitions */ #define QLA8044_MAX_RESET_SEQ_ENTRIES … #define QLA8044_RESTART_TEMPLATE_SIZE … #define QLA8044_RESET_TEMPLATE_ADDR … #define QLA8044_RESET_SEQ_VERSION … /* Reset template entry opcodes */ #define OPCODE_NOP … #define OPCODE_WRITE_LIST … #define OPCODE_READ_WRITE_LIST … #define OPCODE_POLL_LIST … #define OPCODE_POLL_WRITE_LIST … #define OPCODE_READ_MODIFY_WRITE … #define OPCODE_SEQ_PAUSE … #define OPCODE_SEQ_END … #define OPCODE_TMPL_END … #define OPCODE_POLL_READ_LIST … /* Template Header */ #define RESET_TMPLT_HDR_SIGNATURE … #define QLA8044_IDC_DRV_CTRL … #define AF_8044_NO_FW_DUMP … #define MINIDUMP_SIZE_36K … struct qla8044_reset_template_hdr { … } __packed; /* Common Entry Header. */ struct qla8044_reset_entry_hdr { … } __packed; /* Generic poll entry type. */ struct qla8044_poll { … } __packed; /* Read modify write entry type. */ struct qla8044_rmw { … } __packed; /* Generic Entry Item with 2 DWords. */ struct qla8044_entry { … } __packed; /* Generic Entry Item with 4 DWords.*/ struct qla8044_quad_entry { … } __packed; struct qla8044_reset_template { … }; /* Driver_code is for driver to write some info about the entry * currently not used. */ struct qla8044_minidump_entry_hdr { … } __packed; /* Read CRB entry header */ struct qla8044_minidump_entry_crb { … } __packed; struct qla8044_minidump_entry_cache { … } __packed; /* Read OCM */ struct qla8044_minidump_entry_rdocm { … } __packed; /* Read Memory */ struct qla8044_minidump_entry_rdmem { … }; /* Read Memory: For Pex-DMA */ struct qla8044_minidump_entry_rdmem_pex_dma { … } __packed; /* Read ROM */ struct qla8044_minidump_entry_rdrom { … } __packed; /* Mux entry */ struct qla8044_minidump_entry_mux { … } __packed; /* Queue entry */ struct qla8044_minidump_entry_queue { … } __packed; /* POLLRD Entry */ struct qla8044_minidump_entry_pollrd { … } __packed; struct qla8044_minidump_entry_rddfe { … } __packed; struct qla8044_minidump_entry_rdmdio { … } __packed; struct qla8044_minidump_entry_pollwr { … } __packed; /* RDMUX2 Entry */ struct qla8044_minidump_entry_rdmux2 { … } __packed; /* POLLRDMWR Entry */ struct qla8044_minidump_entry_pollrdmwr { … } __packed; /* IDC additional information */ struct qla8044_idc_information { … } __packed; enum qla_regs { … } __packed; #define CRB_REG_INDEX_MAX … #define CRB_CMDPEG_CHECK_RETRY_COUNT … #define CRB_CMDPEG_CHECK_DELAY … /* MiniDump Structures */ /* Driver_code is for driver to write some info about the entry * currently not used. */ #define QLA8044_SS_OCM_WNDREG_INDEX … #define QLA8044_DBG_STATE_ARRAY_LEN … #define QLA8044_DBG_CAP_SIZE_ARRAY_LEN … #define QLA8044_DBG_RSVD_ARRAY_LEN … #define QLA8044_DBG_OCM_WNDREG_ARRAY_LEN … #define QLA8044_SS_PCI_INDEX … #define QLA8044_RDDFE … #define QLA8044_RDMDIO … #define QLA8044_POLLWR … struct qla8044_minidump_template_hdr { … }; struct qla8044_pex_dma_descriptor { … } __packed; #endif
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