/* SPDX-License-Identifier: GPL-2.0-only */ /* * QLogic Fibre Channel HBA Driver * Copyright (c) 2003-2014 QLogic Corporation */ #ifndef __QLA_FW_H #define __QLA_FW_H #include <linux/nvme.h> #include <linux/nvme-fc.h> #include "qla_dsd.h" #define MBS_CHECKSUM_ERROR … #define MBS_INVALID_PRODUCT_KEY … /* * Firmware Options. */ #define FO1_ENABLE_PUREX … #define FO1_DISABLE_LED_CTRL … #define FO1_ENABLE_8016 … #define FO2_ENABLE_SEL_CLASS2 … #define FO3_NO_ABTS_ON_LINKDOWN … #define FO3_HOLD_STS_IOCB … /* * Port Database structure definition for ISP 24xx. */ #define PDO_FORCE_ADISC … #define PDO_FORCE_PLOGI … struct buffer_credit_24xx { … }; #define PORT_DATABASE_24XX_SIZE … struct port_database_24xx { … }; /* * MB 75h returns a list of DB entries similar to port_database_24xx(64B). * However, in this case it returns 1st 40 bytes. */ struct get_name_list_extended { … }; /* MB 75h: This is the short version of the database */ struct get_name_list { … }; struct vp_database_24xx { … }; struct nvram_24xx { … }; /* * ISP Initialization Control Block. * Little endian except where noted. */ #define ICB_VERSION … struct init_cb_24xx { … }; /* * ISP queue - command entry structure definition. */ #define COMMAND_BIDIRECTIONAL … struct cmd_bidir { … }; #define COMMAND_TYPE_6 … struct cmd_type_6 { … }; #define COMMAND_TYPE_7 … struct cmd_type_7 { … }; #define COMMAND_TYPE_CRC_2 … struct cmd_type_crc_2 { … }; /* * ISP queue - status entry structure definition. */ #define STATUS_TYPE … struct sts_entry_24xx { … }; /* * Status entry completion status */ #define CS_DATA_REASSEMBLY_ERROR … #define CS_ABTS_BY_TARGET … #define CS_FW_RESOURCE … #define CS_TASK_MGMT_OVERRUN … #define CS_ABORT_BY_TARGET … /* * ISP queue - marker entry structure definition. */ #define MARKER_TYPE … struct mrk_entry_24xx { … }; /* * ISP queue - CT Pass-Through entry structure definition. */ #define CT_IOCB_TYPE … struct ct_entry_24xx { … }; #define PURX_ELS_HEADER_SIZE … /* * ISP queue - PUREX IOCB entry structure definition */ #define PUREX_IOCB_TYPE … struct purex_entry_24xx { … }; /* * ISP queue - ELS Pass-Through entry structure definition. */ #define ELS_IOCB_TYPE … struct els_entry_24xx { … }; struct els_sts_entry_24xx { … }; /* * ISP queue - Mailbox Command entry structure definition. */ #define MBX_IOCB_TYPE … struct mbx_entry_24xx { … }; #define LOGINOUT_PORT_IOCB_TYPE … struct logio_entry_24xx { … }; #define TSK_MGMT_IOCB_TYPE … struct tsk_mgmt_entry { … }; #define ABORT_IOCB_TYPE … struct abort_entry_24xx { … }; #define ABTS_RCV_TYPE … #define ABTS_RSP_TYPE … struct abts_entry_24xx { … } __packed; /* ABTS payload explanation values */ #define BA_RJT_EXP_NO_ADDITIONAL … #define BA_RJT_EXP_INV_OX_RX_ID … #define BA_RJT_EXP_SEQ_ABORTED … /* ABTS payload reason values */ #define BA_RJT_RSN_INV_CMD_CODE … #define BA_RJT_RSN_LOGICAL_ERROR … #define BA_RJT_RSN_LOGICAL_BUSY … #define BA_RJT_RSN_PROTOCOL_ERROR … #define BA_RJT_RSN_UNABLE_TO_PERFORM … #define BA_RJT_RSN_VENDOR_SPECIFIC … /* FC_F values */ #define FC_TYPE_BLD … #define FC_F_CTL_RSP_CNTXT … #define FC_F_CTL_LAST_SEQ … #define FC_F_CTL_END_SEQ … #define FC_F_CTL_SEQ_INIT … #define FC_ROUTING_BLD … #define FC_R_CTL_BLD_BA_ACC … /* * ISP I/O Register Set structure definitions. */ struct device_reg_24xx { … }; /* RISC-RISC semaphore register PCI offet */ #define RISC_REGISTER_BASE_OFFSET … #define RISC_REGISTER_WINDOW_OFFSET … /* RISC-RISC semaphore/flag register (risc address 0x7016) */ #define RISC_SEMAPHORE … #define RISC_SEMAPHORE_WE … #define RISC_SEMAPHORE_CLR … #define RISC_SEMAPHORE_SET … #define RISC_SEMAPHORE_FORCE … #define RISC_SEMAPHORE_FORCE_WE … #define RISC_SEMAPHORE_FORCE_CLR … #define RISC_SEMAPHORE_FORCE_SET … /* RISC semaphore timeouts (ms) */ #define TIMEOUT_SEMAPHORE … #define TIMEOUT_SEMAPHORE_FORCE … #define TIMEOUT_TOTAL_ELAPSED … /* Trace Control *************************************************************/ #define TC_AEN_DISABLE … #define TC_EFT_ENABLE … #define TC_EFT_DISABLE … #define TC_FCE_ENABLE … #define TC_FCE_OPTIONS … #define TC_FCE_DEFAULT_RX_SIZE … #define TC_FCE_DEFAULT_TX_SIZE … #define TC_FCE_DISABLE … #define TC_FCE_DISABLE_TRACE … /* MID Support ***************************************************************/ #define MIN_MULTI_ID_FABRIC … #define MAX_MULTI_ID_FABRIC … struct mid_conf_entry_24xx { … }; struct mid_init_cb_24xx { … }; struct mid_db_entry_24xx { … }; /* * Virtual Port Control IOCB */ #define VP_CTRL_IOCB_TYPE … struct vp_ctrl_entry_24xx { … }; /* * Modify Virtual Port Configuration IOCB */ #define VP_CONFIG_IOCB_TYPE … struct vp_config_entry_24xx { … }; #define VP_RPT_ID_IOCB_TYPE … enum VP_STATUS { … }; enum VP_FLAGS { … }; struct vp_rpt_id_entry_24xx { … }; #define VF_EVFP_IOCB_TYPE … struct vf_evfp_entry_24xx { … }; /* END MID Support ***********************************************************/ /* Flash Description Table ***************************************************/ struct qla_fdt_layout { … }; /* Flash Layout Table ********************************************************/ struct qla_flt_location { … }; #define FLT_REG_FW … #define FLT_REG_BOOT_CODE … #define FLT_REG_VPD_0 … #define FLT_REG_NVRAM_0 … #define FLT_REG_VPD_1 … #define FLT_REG_NVRAM_1 … #define FLT_REG_VPD_2 … #define FLT_REG_NVRAM_2 … #define FLT_REG_VPD_3 … #define FLT_REG_NVRAM_3 … #define FLT_REG_FDT … #define FLT_REG_FLT … #define FLT_REG_HW_EVENT_0 … #define FLT_REG_HW_EVENT_1 … #define FLT_REG_NPIV_CONF_0 … #define FLT_REG_NPIV_CONF_1 … #define FLT_REG_GOLD_FW … #define FLT_REG_FCP_PRIO_0 … #define FLT_REG_FCP_PRIO_1 … #define FLT_REG_CNA_FW … #define FLT_REG_BOOT_CODE_8044 … #define FLT_REG_FCOE_FW … #define FLT_REG_FCOE_NVRAM_0 … #define FLT_REG_FCOE_NVRAM_1 … /* 27xx */ #define FLT_REG_IMG_PRI_27XX … #define FLT_REG_IMG_SEC_27XX … #define FLT_REG_FW_SEC_27XX … #define FLT_REG_BOOTLOAD_SEC_27XX … #define FLT_REG_VPD_SEC_27XX_0 … #define FLT_REG_VPD_SEC_27XX_1 … #define FLT_REG_VPD_SEC_27XX_2 … #define FLT_REG_VPD_SEC_27XX_3 … #define FLT_REG_NVME_PARAMS_27XX … /* 28xx */ #define FLT_REG_AUX_IMG_PRI_28XX … #define FLT_REG_AUX_IMG_SEC_28XX … #define FLT_REG_VPD_SEC_28XX_0 … #define FLT_REG_VPD_SEC_28XX_1 … #define FLT_REG_VPD_SEC_28XX_2 … #define FLT_REG_VPD_SEC_28XX_3 … #define FLT_REG_NVRAM_SEC_28XX_0 … #define FLT_REG_NVRAM_SEC_28XX_1 … #define FLT_REG_NVRAM_SEC_28XX_2 … #define FLT_REG_NVRAM_SEC_28XX_3 … #define FLT_REG_MPI_PRI_28XX … #define FLT_REG_MPI_SEC_28XX … #define FLT_REG_PEP_PRI_28XX … #define FLT_REG_PEP_SEC_28XX … #define FLT_REG_NVME_PARAMS_PRI_28XX … #define FLT_REG_NVME_PARAMS_SEC_28XX … struct qla_flt_region { … }; struct qla_flt_header { … }; #define FLT_REGION_SIZE … #define FLT_MAX_REGIONS … #define FLT_REGIONS_SIZE … /* Flash NPIV Configuration Table ********************************************/ struct qla_npiv_header { … }; struct qla_npiv_entry { … }; /* 84XX Support **************************************************************/ #define MBA_ISP84XX_ALERT … #define A84_PANIC_RECOVERY … #define A84_OP_LOGIN_COMPLETE … #define A84_DIAG_LOGIN_COMPLETE … #define A84_GOLD_LOGIN_COMPLETE … #define MBC_ISP84XX_RESET … #define FSTATE_REMOTE_FC_DOWN … #define FSTATE_NSL_LINK_DOWN … #define FSTATE_IS_DIAG_FW … #define FSTATE_LOGGED_IN … #define FSTATE_WAITING_FOR_VERIFY … #define VERIFY_CHIP_IOCB_TYPE … struct verify_chip_entry_84xx { … }; struct verify_chip_rsp_84xx { … }; #define ACCESS_CHIP_IOCB_TYPE … struct access_chip_84xx { … }; struct access_chip_rsp_84xx { … }; /* 81XX Support **************************************************************/ #define MBA_DCBX_START … #define MBA_DCBX_COMPLETE … #define MBA_FCF_CONF_ERR … #define MBA_DCBX_PARAM_UPDATE … #define MBA_IDC_COMPLETE … #define MBA_IDC_NOTIFY … #define MBA_IDC_TIME_EXT … #define MBC_IDC_ACK … #define MBC_RESTART_MPI_FW … #define MBC_FLASH_ACCESS_CTRL … #define MBC_GET_XGMAC_STATS … #define MBC_GET_DCBX_PARAMS … /* * ISP83xx mailbox commands */ #define MBC_WRITE_REMOTE_REG … #define MBC_READ_REMOTE_REG … #define MBC_RESTART_NIC_FIRMWARE … #define MBC_SET_ACCESS_CONTROL … /* Flash access control option field bit definitions */ #define FAC_OPT_FORCE_SEMAPHORE … #define FAC_OPT_REQUESTOR_ID … #define FAC_OPT_CMD_SUBCODE … /* Flash access control command subcodes */ #define FAC_OPT_CMD_WRITE_PROTECT … #define FAC_OPT_CMD_WRITE_ENABLE … #define FAC_OPT_CMD_ERASE_SECTOR … #define FAC_OPT_CMD_LOCK_SEMAPHORE … #define FAC_OPT_CMD_UNLOCK_SEMAPHORE … #define FAC_OPT_CMD_GET_SECTOR_SIZE … /* enhanced features bit definitions */ #define NEF_LR_DIST_ENABLE … /* LR Distance bit positions */ #define LR_DIST_NV_POS … #define LR_DIST_NV_MASK … #define LR_DIST_FW_POS … /* FAC semaphore defines */ #define FAC_SEMAPHORE_UNLOCK … #define FAC_SEMAPHORE_LOCK … struct nvram_81xx { … }; /* * ISP Initialization Control Block. * Little endian except where noted. */ #define ICB_VERSION … struct init_cb_81xx { … }; struct mid_init_cb_81xx { … }; struct ex_init_cb_81xx { … }; #define FARX_ACCESS_FLASH_CONF_81XX … #define FARX_ACCESS_FLASH_DATA_81XX … #define FARX_ACCESS_FLASH_CONF_28XX … #define FARX_ACCESS_FLASH_DATA_28XX … /* FCP priority config defines *************************************/ /* operations */ #define QLFC_FCP_PRIO_DISABLE … #define QLFC_FCP_PRIO_ENABLE … #define QLFC_FCP_PRIO_GET_CONFIG … #define QLFC_FCP_PRIO_SET_CONFIG … struct qla_fcp_prio_entry { … }; struct qla_fcp_prio_cfg { … }; #define FCP_PRIO_CFG_SIZE … /* 25XX Support ****************************************************/ #define FA_FCP_PRIO0_ADDR_25 … #define FA_FCP_PRIO1_ADDR_25 … /* 81XX Flash locations -- occupies second 2MB region. */ #define FA_BOOT_CODE_ADDR_81 … #define FA_RISC_CODE_ADDR_81 … #define FA_FW_AREA_ADDR_81 … #define FA_VPD_NVRAM_ADDR_81 … #define FA_VPD0_ADDR_81 … #define FA_VPD1_ADDR_81 … #define FA_NVRAM0_ADDR_81 … #define FA_NVRAM1_ADDR_81 … #define FA_FEATURE_ADDR_81 … #define FA_FLASH_DESCR_ADDR_81 … #define FA_FLASH_LAYOUT_ADDR_81 … #define FA_HW_EVENT0_ADDR_81 … #define FA_HW_EVENT1_ADDR_81 … #define FA_NPIV_CONF0_ADDR_81 … #define FA_NPIV_CONF1_ADDR_81 … /* 83XX Flash locations -- occupies second 8MB region. */ #define FA_FLASH_LAYOUT_ADDR_83 … #define FA_FLASH_LAYOUT_ADDR_28 … #define NVRAM_DUAL_FCP_NVME_FLAG_OFFSET … #endif
Codebase Browser
linux