/******************************************************************* * This file is part of the Emulex Linux Device Driver for * * Fibre Channel Host Bus Adapters. * * Copyright (C) 2017-2024 Broadcom. All Rights Reserved. The term * * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * * Copyright (C) 2009-2016 Emulex. All rights reserved. * * EMULEX and SLI are trademarks of Emulex. * * www.broadcom.com * * * * This program is free software; you can redistribute it and/or * * modify it under the terms of version 2 of the GNU General * * Public License as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful. * * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * * TO BE LEGALLY INVALID. See the GNU General Public License for * * more details, a copy of which can be found in the file COPYING * * included with this package. * *******************************************************************/ #include <uapi/scsi/fc/fc_fs.h> #include <uapi/scsi/fc/fc_els.h> /* Macros to deal with bit fields. Each bit field must have 3 #defines * associated with it (_SHIFT, _MASK, and _WORD). * EG. For a bit field that is in the 7th bit of the "field4" field of a * structure and is 2 bits in size the following #defines must exist: * struct temp { * uint32_t field1; * uint32_t field2; * uint32_t field3; * uint32_t field4; * #define example_bit_field_SHIFT 7 * #define example_bit_field_MASK 0x03 * #define example_bit_field_WORD field4 * uint32_t field5; * }; * Then the macros below may be used to get or set the value of that field. * EG. To get the value of the bit field from the above example: * struct temp t1; * value = bf_get(example_bit_field, &t1); * And then to set that bit field: * bf_set(example_bit_field, &t1, 2); * Or clear that bit field: * bf_set(example_bit_field, &t1, 0); */ #define bf_get_be32(name, ptr) … #define bf_get_le32(name, ptr) … #define bf_get(name, ptr) … #define bf_set_le32(name, ptr, value) … #define bf_set(name, ptr, value) … #define get_wqe_reqtag(x) … #define get_wqe_tmo(x) … #define get_job_ulpword(x, y) … #define set_job_ulpstatus(x, y) … #define set_job_ulpword4(x, y) … struct dma_address { … }; struct lpfc_sli_intf { … }; #define LPFC_SLI4_MBX_EMBED … #define LPFC_SLI4_MBX_NEMBED … #define LPFC_SLI4_MB_WORD_COUNT … #define LPFC_MAX_MQ_PAGE … #define LPFC_MAX_WQ_PAGE_V0 … #define LPFC_MAX_WQ_PAGE … #define LPFC_MAX_RQ_PAGE … #define LPFC_MAX_CQ_PAGE … #define LPFC_MAX_EQ_PAGE … #define LPFC_VIR_FUNC_MAX … #define LPFC_PCI_FUNC_MAX … #define LPFC_VFR_PAGE_SIZE … /* Define SLI4 Alignment requirements. */ #define LPFC_ALIGN_16_BYTE … #define LPFC_ALIGN_64_BYTE … #define SLI4_PAGE_SIZE … /* Define SLI4 specific definitions. */ #define LPFC_MQ_CQE_BYTE_OFFSET … #define LPFC_MBX_CMD_HDR_LENGTH … #define LPFC_MBX_ERROR_RANGE … #define LPFC_BMBX_BIT1_ADDR_HI … #define LPFC_BMBX_BIT1_ADDR_LO … #define LPFC_RPI_HDR_COUNT … #define LPFC_HDR_TEMPLATE_SIZE … #define LPFC_RPI_ALLOC_ERROR … #define LPFC_FCF_RECORD_WD_CNT … #define LPFC_ENTIRE_FCF_DATABASE … #define LPFC_DFLT_FCF_INDEX … /* Virtual function numbers */ #define LPFC_VF0 … #define LPFC_VF1 … #define LPFC_VF2 … #define LPFC_VF3 … #define LPFC_VF4 … #define LPFC_VF5 … #define LPFC_VF6 … #define LPFC_VF7 … #define LPFC_VF8 … #define LPFC_VF9 … #define LPFC_VF10 … #define LPFC_VF11 … #define LPFC_VF12 … #define LPFC_VF13 … #define LPFC_VF14 … #define LPFC_VF15 … #define LPFC_VF16 … #define LPFC_VF17 … #define LPFC_VF18 … #define LPFC_VF19 … #define LPFC_VF20 … #define LPFC_VF21 … #define LPFC_VF22 … #define LPFC_VF23 … #define LPFC_VF24 … #define LPFC_VF25 … #define LPFC_VF26 … #define LPFC_VF27 … #define LPFC_VF28 … #define LPFC_VF29 … #define LPFC_VF30 … #define LPFC_VF31 … /* PCI function numbers */ #define LPFC_PCI_FUNC0 … #define LPFC_PCI_FUNC1 … #define LPFC_PCI_FUNC2 … #define LPFC_PCI_FUNC3 … #define LPFC_PCI_FUNC4 … /* SLI4 interface type-2 PDEV_CTL register */ #define LPFC_CTL_PDEV_CTL_OFFSET … #define LPFC_CTL_PDEV_CTL_DRST … #define LPFC_CTL_PDEV_CTL_FRST … #define LPFC_CTL_PDEV_CTL_DD … #define LPFC_CTL_PDEV_CTL_LC … #define LPFC_CTL_PDEV_CTL_FRL_ALL … #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE … #define LPFC_CTL_PDEV_CTL_FRL_NIC … #define LPFC_CTL_PDEV_CTL_DDL_RAS … #define LPFC_FW_DUMP_REQUEST … /* Active interrupt test count */ #define LPFC_ACT_INTR_CNT … /* Algrithmns for scheduling FCP commands to WQs */ #define LPFC_FCP_SCHED_BY_HDWQ … #define LPFC_FCP_SCHED_BY_CPU … /* Algrithmns for NameServer Query after RSCN */ #define LPFC_NS_QUERY_GID_FT … #define LPFC_NS_QUERY_GID_PT … /* Delay Multiplier constant */ #define LPFC_DMULT_CONST … #define LPFC_DMULT_MAX … /* Configuration of Interrupts / sec for entire HBA port */ #define LPFC_MIN_IMAX … #define LPFC_MAX_IMAX … #define LPFC_DEF_IMAX … #define LPFC_MAX_AUTO_EQ_DELAY … #define LPFC_EQ_DELAY_STEP … #define LPFC_EQD_ISR_TRIGGER … /* 1s intervals */ #define LPFC_EQ_DELAY_MSECS … #define LPFC_MIN_CPU_MAP … #define LPFC_MAX_CPU_MAP … #define LPFC_HBA_CPU_MAP … /* PORT_CAPABILITIES constants. */ #define LPFC_MAX_SUPPORTED_PAGES … enum ulp_bde64_word3 { … }; struct ulp_bde64_le { … }; struct ulp_bde64 { … }; /* Maximun size of immediate data that can fit into a 128 byte WQE */ #define LPFC_MAX_BDE_IMM_SIZE … struct lpfc_sli4_flags { … }; struct sli4_bls_rsp { … }; /* event queue entry structure */ struct lpfc_eqe { … }; /* completion queue entry structure (common fields for all cqe types) */ struct lpfc_cqe { … }; /* Completion Queue Entry Status Codes */ #define CQE_STATUS_SUCCESS … #define CQE_STATUS_FCP_RSP_FAILURE … #define CQE_STATUS_REMOTE_STOP … #define CQE_STATUS_LOCAL_REJECT … #define CQE_STATUS_NPORT_RJT … #define CQE_STATUS_FABRIC_RJT … #define CQE_STATUS_NPORT_BSY … #define CQE_STATUS_FABRIC_BSY … #define CQE_STATUS_INTERMED_RSP … #define CQE_STATUS_LS_RJT … #define CQE_STATUS_CMD_REJECT … #define CQE_STATUS_FCP_TGT_LENCHECK … #define CQE_STATUS_NEED_BUFF_ENTRY … #define CQE_STATUS_DI_ERROR … /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ #define CQE_HW_STATUS_NO_ERR … #define CQE_HW_STATUS_UNDERRUN … #define CQE_HW_STATUS_OVERRUN … /* Completion Queue Entry Codes */ #define CQE_CODE_COMPL_WQE … #define CQE_CODE_RELEASE_WQE … #define CQE_CODE_RECEIVE … #define CQE_CODE_XRI_ABORTED … #define CQE_CODE_RECEIVE_V1 … #define CQE_CODE_NVME_ERSP … /* * Define mask value for xri_aborted and wcqe completed CQE extended status. * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . */ #define WCQE_PARAM_MASK … /* completion queue entry for wqe completions */ struct lpfc_wcqe_complete { … }; /* completion queue entry for wqe release */ struct lpfc_wcqe_release { … }; struct sli4_wcqe_xri_aborted { … }; /* completion queue entry structure for rqe completion */ struct lpfc_rcqe { … }; struct lpfc_rqe { … }; /* buffer descriptors */ struct lpfc_bde4 { … }; struct lpfc_register { … }; #define LPFC_PORT_SEM_UE_RECOVERABLE … #define LPFC_PORT_SEM_MASK … /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ #define LPFC_UERR_STATUS_HI … #define LPFC_UERR_STATUS_LO … #define LPFC_UE_MASK_HI … #define LPFC_UE_MASK_LO … /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ #define LPFC_SLI_INTF … #define LPFC_SLI_ASIC_VER … #define LPFC_CTL_PORT_SEM_OFFSET … #define lpfc_port_smphr_perr_SHIFT … #define lpfc_port_smphr_perr_MASK … #define lpfc_port_smphr_perr_WORD … #define lpfc_port_smphr_sfi_SHIFT … #define lpfc_port_smphr_sfi_MASK … #define lpfc_port_smphr_sfi_WORD … #define lpfc_port_smphr_nip_SHIFT … #define lpfc_port_smphr_nip_MASK … #define lpfc_port_smphr_nip_WORD … #define lpfc_port_smphr_ipc_SHIFT … #define lpfc_port_smphr_ipc_MASK … #define lpfc_port_smphr_ipc_WORD … #define lpfc_port_smphr_scr1_SHIFT … #define lpfc_port_smphr_scr1_MASK … #define lpfc_port_smphr_scr1_WORD … #define lpfc_port_smphr_scr2_SHIFT … #define lpfc_port_smphr_scr2_MASK … #define lpfc_port_smphr_scr2_WORD … #define lpfc_port_smphr_host_scratch_SHIFT … #define lpfc_port_smphr_host_scratch_MASK … #define lpfc_port_smphr_host_scratch_WORD … #define lpfc_port_smphr_port_status_SHIFT … #define lpfc_port_smphr_port_status_MASK … #define lpfc_port_smphr_port_status_WORD … #define LPFC_POST_STAGE_POWER_ON_RESET … #define LPFC_POST_STAGE_AWAITING_HOST_RDY … #define LPFC_POST_STAGE_HOST_RDY … #define LPFC_POST_STAGE_BE_RESET … #define LPFC_POST_STAGE_SEEPROM_CS_START … #define LPFC_POST_STAGE_SEEPROM_CS_DONE … #define LPFC_POST_STAGE_DDR_CONFIG_START … #define LPFC_POST_STAGE_DDR_CONFIG_DONE … #define LPFC_POST_STAGE_DDR_CALIBRATE_START … #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE … #define LPFC_POST_STAGE_DDR_TEST_START … #define LPFC_POST_STAGE_DDR_TEST_DONE … #define LPFC_POST_STAGE_REDBOOT_INIT_START … #define LPFC_POST_STAGE_REDBOOT_INIT_DONE … #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START … #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE … #define LPFC_POST_STAGE_ARMFW_START … #define LPFC_POST_STAGE_DHCP_QUERY_START … #define LPFC_POST_STAGE_DHCP_QUERY_DONE … #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START … #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE … #define LPFC_POST_STAGE_RC_OPTION_SET … #define LPFC_POST_STAGE_SWITCH_LINK … #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE … #define LPFC_POST_STAGE_PERFROM_TFTP … #define LPFC_POST_STAGE_PARSE_XML … #define LPFC_POST_STAGE_DOWNLOAD_IMAGE … #define LPFC_POST_STAGE_FLASH_IMAGE … #define LPFC_POST_STAGE_RC_DONE … #define LPFC_POST_STAGE_REBOOT_SYSTEM … #define LPFC_POST_STAGE_MAC_ADDRESS … #define LPFC_POST_STAGE_PORT_READY … #define LPFC_POST_STAGE_PORT_UE … #define LPFC_CTL_PORT_STA_OFFSET … #define lpfc_sliport_status_err_SHIFT … #define lpfc_sliport_status_err_MASK … #define lpfc_sliport_status_err_WORD … #define lpfc_sliport_status_end_SHIFT … #define lpfc_sliport_status_end_MASK … #define lpfc_sliport_status_end_WORD … #define lpfc_sliport_status_oti_SHIFT … #define lpfc_sliport_status_oti_MASK … #define lpfc_sliport_status_oti_WORD … #define lpfc_sliport_status_dip_SHIFT … #define lpfc_sliport_status_dip_MASK … #define lpfc_sliport_status_dip_WORD … #define lpfc_sliport_status_rn_SHIFT … #define lpfc_sliport_status_rn_MASK … #define lpfc_sliport_status_rn_WORD … #define lpfc_sliport_status_rdy_SHIFT … #define lpfc_sliport_status_rdy_MASK … #define lpfc_sliport_status_rdy_WORD … #define lpfc_sliport_status_pldv_SHIFT … #define lpfc_sliport_status_pldv_MASK … #define lpfc_sliport_status_pldv_WORD … #define CFG_PLD … #define MAX_IF_TYPE_2_RESETS … #define LPFC_CTL_PORT_CTL_OFFSET … #define lpfc_sliport_ctrl_end_SHIFT … #define lpfc_sliport_ctrl_end_MASK … #define lpfc_sliport_ctrl_end_WORD … #define LPFC_SLIPORT_LITTLE_ENDIAN … #define LPFC_SLIPORT_BIG_ENDIAN … #define lpfc_sliport_ctrl_ip_SHIFT … #define lpfc_sliport_ctrl_ip_MASK … #define lpfc_sliport_ctrl_ip_WORD … #define LPFC_SLIPORT_INIT_PORT … #define LPFC_CTL_PORT_ER1_OFFSET … #define LPFC_CTL_PORT_ER2_OFFSET … #define LPFC_CTL_PORT_EQ_DELAY_OFFSET … #define lpfc_sliport_eqdelay_delay_SHIFT … #define lpfc_sliport_eqdelay_delay_MASK … #define lpfc_sliport_eqdelay_delay_WORD … #define lpfc_sliport_eqdelay_id_SHIFT … #define lpfc_sliport_eqdelay_id_MASK … #define lpfc_sliport_eqdelay_id_WORD … #define LPFC_SEC_TO_USEC … #define LPFC_SEC_TO_MSEC … #define LPFC_MSECS_TO_SECS(msecs) … /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically * reside in BAR 2. */ #define LPFC_SLIPORT_IF0_SMPHR … #define LPFC_IMR_MASK_ALL … #define LPFC_ISCR_CLEAR_ALL … #define LPFC_HST_ISR0 … #define LPFC_HST_ISR1 … #define LPFC_HST_ISR2 … #define LPFC_HST_ISR3 … #define LPFC_HST_ISR4 … #define LPFC_HST_IMR0 … #define LPFC_HST_IMR1 … #define LPFC_HST_IMR2 … #define LPFC_HST_IMR3 … #define LPFC_HST_IMR4 … #define LPFC_HST_ISCR0 … #define LPFC_HST_ISCR1 … #define LPFC_HST_ISCR2 … #define LPFC_HST_ISCR3 … #define LPFC_HST_ISCR4 … #define LPFC_SLI4_INTR0 … #define LPFC_SLI4_INTR1 … #define LPFC_SLI4_INTR2 … #define LPFC_SLI4_INTR3 … #define LPFC_SLI4_INTR4 … #define LPFC_SLI4_INTR5 … #define LPFC_SLI4_INTR6 … #define LPFC_SLI4_INTR7 … #define LPFC_SLI4_INTR8 … #define LPFC_SLI4_INTR9 … #define LPFC_SLI4_INTR10 … #define LPFC_SLI4_INTR11 … #define LPFC_SLI4_INTR12 … #define LPFC_SLI4_INTR13 … #define LPFC_SLI4_INTR14 … #define LPFC_SLI4_INTR15 … #define LPFC_SLI4_INTR16 … #define LPFC_SLI4_INTR17 … #define LPFC_SLI4_INTR18 … #define LPFC_SLI4_INTR19 … #define LPFC_SLI4_INTR20 … #define LPFC_SLI4_INTR21 … #define LPFC_SLI4_INTR22 … #define LPFC_SLI4_INTR23 … #define LPFC_SLI4_INTR24 … #define LPFC_SLI4_INTR25 … #define LPFC_SLI4_INTR26 … #define LPFC_SLI4_INTR27 … #define LPFC_SLI4_INTR28 … #define LPFC_SLI4_INTR29 … #define LPFC_SLI4_INTR30 … #define LPFC_SLI4_INTR31 … /* * The Doorbell registers defined here exist in different BAR * register sets depending on the UCNA Port's reported if_type * value. For UCNA ports running SLI4 and if_type 0, they reside in * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in * BAR0. For FC ports running SLI4 and if_type 6, they reside in * BAR2. The offsets and base address are different, so the driver * has to compute the register addresses accordingly */ #define LPFC_ULP0_RQ_DOORBELL … #define LPFC_ULP1_RQ_DOORBELL … #define LPFC_IF6_RQ_DOORBELL … #define lpfc_rq_db_list_fm_num_posted_SHIFT … #define lpfc_rq_db_list_fm_num_posted_MASK … #define lpfc_rq_db_list_fm_num_posted_WORD … #define lpfc_rq_db_list_fm_index_SHIFT … #define lpfc_rq_db_list_fm_index_MASK … #define lpfc_rq_db_list_fm_index_WORD … #define lpfc_rq_db_list_fm_id_SHIFT … #define lpfc_rq_db_list_fm_id_MASK … #define lpfc_rq_db_list_fm_id_WORD … #define lpfc_rq_db_ring_fm_num_posted_SHIFT … #define lpfc_rq_db_ring_fm_num_posted_MASK … #define lpfc_rq_db_ring_fm_num_posted_WORD … #define lpfc_rq_db_ring_fm_id_SHIFT … #define lpfc_rq_db_ring_fm_id_MASK … #define lpfc_rq_db_ring_fm_id_WORD … #define LPFC_ULP0_WQ_DOORBELL … #define LPFC_ULP1_WQ_DOORBELL … #define lpfc_wq_db_list_fm_num_posted_SHIFT … #define lpfc_wq_db_list_fm_num_posted_MASK … #define lpfc_wq_db_list_fm_num_posted_WORD … #define lpfc_wq_db_list_fm_index_SHIFT … #define lpfc_wq_db_list_fm_index_MASK … #define lpfc_wq_db_list_fm_index_WORD … #define lpfc_wq_db_list_fm_id_SHIFT … #define lpfc_wq_db_list_fm_id_MASK … #define lpfc_wq_db_list_fm_id_WORD … #define lpfc_wq_db_ring_fm_num_posted_SHIFT … #define lpfc_wq_db_ring_fm_num_posted_MASK … #define lpfc_wq_db_ring_fm_num_posted_WORD … #define lpfc_wq_db_ring_fm_id_SHIFT … #define lpfc_wq_db_ring_fm_id_MASK … #define lpfc_wq_db_ring_fm_id_WORD … #define LPFC_IF6_WQ_DOORBELL … #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT … #define lpfc_if6_wq_db_list_fm_num_posted_MASK … #define lpfc_if6_wq_db_list_fm_num_posted_WORD … #define lpfc_if6_wq_db_list_fm_dpp_SHIFT … #define lpfc_if6_wq_db_list_fm_dpp_MASK … #define lpfc_if6_wq_db_list_fm_dpp_WORD … #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT … #define lpfc_if6_wq_db_list_fm_dpp_id_MASK … #define lpfc_if6_wq_db_list_fm_dpp_id_WORD … #define lpfc_if6_wq_db_list_fm_id_SHIFT … #define lpfc_if6_wq_db_list_fm_id_MASK … #define lpfc_if6_wq_db_list_fm_id_WORD … #define LPFC_EQCQ_DOORBELL … #define lpfc_eqcq_doorbell_se_SHIFT … #define lpfc_eqcq_doorbell_se_MASK … #define lpfc_eqcq_doorbell_se_WORD … #define LPFC_EQCQ_SOLICIT_ENABLE_OFF … #define LPFC_EQCQ_SOLICIT_ENABLE_ON … #define lpfc_eqcq_doorbell_arm_SHIFT … #define lpfc_eqcq_doorbell_arm_MASK … #define lpfc_eqcq_doorbell_arm_WORD … #define lpfc_eqcq_doorbell_num_released_SHIFT … #define lpfc_eqcq_doorbell_num_released_MASK … #define lpfc_eqcq_doorbell_num_released_WORD … #define lpfc_eqcq_doorbell_qt_SHIFT … #define lpfc_eqcq_doorbell_qt_MASK … #define lpfc_eqcq_doorbell_qt_WORD … #define LPFC_QUEUE_TYPE_COMPLETION … #define LPFC_QUEUE_TYPE_EVENT … #define lpfc_eqcq_doorbell_eqci_SHIFT … #define lpfc_eqcq_doorbell_eqci_MASK … #define lpfc_eqcq_doorbell_eqci_WORD … #define lpfc_eqcq_doorbell_cqid_lo_SHIFT … #define lpfc_eqcq_doorbell_cqid_lo_MASK … #define lpfc_eqcq_doorbell_cqid_lo_WORD … #define lpfc_eqcq_doorbell_cqid_hi_SHIFT … #define lpfc_eqcq_doorbell_cqid_hi_MASK … #define lpfc_eqcq_doorbell_cqid_hi_WORD … #define lpfc_eqcq_doorbell_eqid_lo_SHIFT … #define lpfc_eqcq_doorbell_eqid_lo_MASK … #define lpfc_eqcq_doorbell_eqid_lo_WORD … #define lpfc_eqcq_doorbell_eqid_hi_SHIFT … #define lpfc_eqcq_doorbell_eqid_hi_MASK … #define lpfc_eqcq_doorbell_eqid_hi_WORD … #define LPFC_CQID_HI_FIELD_SHIFT … #define LPFC_EQID_HI_FIELD_SHIFT … #define LPFC_IF6_CQ_DOORBELL … #define lpfc_if6_cq_doorbell_se_SHIFT … #define lpfc_if6_cq_doorbell_se_MASK … #define lpfc_if6_cq_doorbell_se_WORD … #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF … #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON … #define lpfc_if6_cq_doorbell_arm_SHIFT … #define lpfc_if6_cq_doorbell_arm_MASK … #define lpfc_if6_cq_doorbell_arm_WORD … #define lpfc_if6_cq_doorbell_num_released_SHIFT … #define lpfc_if6_cq_doorbell_num_released_MASK … #define lpfc_if6_cq_doorbell_num_released_WORD … #define lpfc_if6_cq_doorbell_cqid_SHIFT … #define lpfc_if6_cq_doorbell_cqid_MASK … #define lpfc_if6_cq_doorbell_cqid_WORD … #define LPFC_IF6_EQ_DOORBELL … #define lpfc_if6_eq_doorbell_io_SHIFT … #define lpfc_if6_eq_doorbell_io_MASK … #define lpfc_if6_eq_doorbell_io_WORD … #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF … #define LPFC_IF6_EQ_INTR_OVERRIDE_ON … #define lpfc_if6_eq_doorbell_arm_SHIFT … #define lpfc_if6_eq_doorbell_arm_MASK … #define lpfc_if6_eq_doorbell_arm_WORD … #define lpfc_if6_eq_doorbell_num_released_SHIFT … #define lpfc_if6_eq_doorbell_num_released_MASK … #define lpfc_if6_eq_doorbell_num_released_WORD … #define lpfc_if6_eq_doorbell_eqid_SHIFT … #define lpfc_if6_eq_doorbell_eqid_MASK … #define lpfc_if6_eq_doorbell_eqid_WORD … #define LPFC_BMBX … #define lpfc_bmbx_addr_SHIFT … #define lpfc_bmbx_addr_MASK … #define lpfc_bmbx_addr_WORD … #define lpfc_bmbx_hi_SHIFT … #define lpfc_bmbx_hi_MASK … #define lpfc_bmbx_hi_WORD … #define lpfc_bmbx_rdy_SHIFT … #define lpfc_bmbx_rdy_MASK … #define lpfc_bmbx_rdy_WORD … #define LPFC_MQ_DOORBELL … #define LPFC_IF6_MQ_DOORBELL … #define lpfc_mq_doorbell_num_posted_SHIFT … #define lpfc_mq_doorbell_num_posted_MASK … #define lpfc_mq_doorbell_num_posted_WORD … #define lpfc_mq_doorbell_id_SHIFT … #define lpfc_mq_doorbell_id_MASK … #define lpfc_mq_doorbell_id_WORD … struct lpfc_sli4_cfg_mhdr { … }; lpfc_sli4_cfg_shdr; /* Mailbox Header structures. * struct mbox_header is defined for first generation SLI4_CFG mailbox * calls deployed for BE-based ports. * * struct sli4_mbox_header is defined for second generation SLI4 * ports that don't deploy the SLI4_CFG mechanism. */ struct mbox_header { … }; #define LPFC_EXTENT_LOCAL … #define LPFC_TIMEOUT_DEFAULT … #define LPFC_EXTENT_VERSION_DEFAULT … /* Subsystem Definitions */ #define LPFC_MBOX_SUBSYSTEM_NA … #define LPFC_MBOX_SUBSYSTEM_COMMON … #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL … #define LPFC_MBOX_SUBSYSTEM_FCOE … /* Device Specific Definitions */ /* The HOST ENDIAN defines are in Big Endian format. */ #define HOST_ENDIAN_LOW_WORD0 … #define HOST_ENDIAN_HIGH_WORD1 … /* Common Opcodes */ #define LPFC_MBOX_OPCODE_NA … #define LPFC_MBOX_OPCODE_CQ_CREATE … #define LPFC_MBOX_OPCODE_EQ_CREATE … #define LPFC_MBOX_OPCODE_MQ_CREATE … #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES … #define LPFC_MBOX_OPCODE_NOP … #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY … #define LPFC_MBOX_OPCODE_MQ_DESTROY … #define LPFC_MBOX_OPCODE_CQ_DESTROY … #define LPFC_MBOX_OPCODE_EQ_DESTROY … #define LPFC_MBOX_OPCODE_QUERY_FW_CFG … #define LPFC_MBOX_OPCODE_FUNCTION_RESET … #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG … #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG … #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG … #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG … #define LPFC_MBOX_OPCODE_GET_PORT_NAME … #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT … #define LPFC_MBOX_OPCODE_GET_VPD_DATA … #define LPFC_MBOX_OPCODE_SET_HOST_DATA … #define LPFC_MBOX_OPCODE_SEND_ACTIVATION … #define LPFC_MBOX_OPCODE_RESET_LICENSES … #define LPFC_MBOX_OPCODE_REG_CONGESTION_BUF … #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO … #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT … #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT … #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT … #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG … #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES … #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG … #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG … #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST … #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE … #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG … #define LPFC_MBOX_OPCODE_READ_OBJECT … #define LPFC_MBOX_OPCODE_WRITE_OBJECT … #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST … #define LPFC_MBOX_OPCODE_DELETE_OBJECT … #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS … #define LPFC_MBOX_OPCODE_SET_FEATURES … /* FCoE Opcodes */ #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE … #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY … #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES … #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES … #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE … #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY … #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE … #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF … #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF … #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE … #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF … #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET … #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS … #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE … #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK … #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE … /* Low level Opcodes */ #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION … /* Mailbox command structures */ struct eq_context { … }; struct eq_delay_info { … }; #define LPFC_MAX_EQ_DELAY_EQID_CNT … struct sgl_page_pairs { … }; struct lpfc_mbx_post_sgl_pages { … }; /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ struct lpfc_mbx_post_uembed_sgl_page1 { … }; struct lpfc_mbx_sge { … }; struct lpfc_mbx_host_buf { … }; struct lpfc_mbx_nembed_cmd { … }; struct lpfc_mbx_nembed_sge_virt { … }; #define LPFC_MBX_OBJECT_NAME_LEN_DW … struct lpfc_mbx_read_object { … }; struct lpfc_mbx_eq_create { … }; struct lpfc_mbx_modify_eq_delay { … }; struct lpfc_mbx_eq_destroy { … }; struct lpfc_mbx_nop { … }; struct lpfc_mbx_set_ras_fwlog { … }; struct cq_context { … }; struct lpfc_mbx_cq_create { … }; struct lpfc_mbx_cq_create_set { … }; struct lpfc_mbx_cq_destroy { … }; struct wq_context { … }; struct lpfc_mbx_wq_create { … }; struct lpfc_mbx_wq_destroy { … }; #define LPFC_HDR_BUF_SIZE … #define LPFC_DATA_BUF_SIZE … #define LPFC_NVMET_DATA_BUF_SIZE … struct rq_context { … }; struct lpfc_mbx_rq_create { … }; struct lpfc_mbx_rq_create_v2 { … }; struct lpfc_mbx_rq_destroy { … }; struct mq_context { … }; struct lpfc_mbx_mq_create { … }; struct lpfc_mbx_mq_create_ext { … }; struct lpfc_mbx_mq_destroy { … }; /* Start Gen 2 SLI4 Mailbox definitions: */ /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ #define LPFC_RSC_TYPE_FCOE_VFI … #define LPFC_RSC_TYPE_FCOE_VPI … #define LPFC_RSC_TYPE_FCOE_RPI … #define LPFC_RSC_TYPE_FCOE_XRI … struct lpfc_mbx_get_rsrc_extent_info { … }; struct lpfc_mbx_query_fw_config { … }; struct lpfc_mbx_set_beacon_config { … }; struct lpfc_id_range { … }; struct lpfc_mbx_set_link_diag_state { … }; struct lpfc_mbx_set_link_diag_loopback { … }; struct lpfc_mbx_run_link_diag_test { … }; /* * struct lpfc_mbx_alloc_rsrc_extents: * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires * 6 words of header + 4 words of shared subcommand header + * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. * * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes * for extents payload. * * 212/2 (bytes per extent) = 106 extents. * 106/2 (extents per word) = 53 words. * lpfc_id_range id is statically size to 53. * * This mailbox definition is used for ALLOC or GET_ALLOCATED * extent ranges. For ALLOC, the type and cnt are required. * For GET_ALLOCATED, only the type is required. */ struct lpfc_mbx_alloc_rsrc_extents { … }; /* * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this * structure shares the same SHIFT/MASK/WORD defines provided in the * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in * the structures defined above. This non-embedded structure provides for the * maximum number of extents supported by the port. */ struct lpfc_mbx_nembed_rsrc_extent { … }; struct lpfc_mbx_dealloc_rsrc_extents { … }; /* Start SLI4 FCoE specific mbox structures. */ struct lpfc_mbx_post_hdr_tmpl { … }; struct sli4_sge { … }; struct sli4_sge_le { … }; struct sli4_hybrid_sgl { … }; struct fcp_cmd_rsp_buf { … }; struct sli4_sge_diseed { … }; struct fcf_record { … }; struct lpfc_mbx_read_fcf_tbl { … }; struct lpfc_mbx_add_fcf_tbl_entry { … }; struct lpfc_mbx_del_fcf_tbl_entry { … }; struct lpfc_mbx_redisc_fcf_tbl { … }; /* Status field for embedded SLI_CONFIG mailbox command */ #define STATUS_SUCCESS … #define STATUS_FAILED … #define STATUS_ILLEGAL_REQUEST … #define STATUS_ILLEGAL_FIELD … #define STATUS_INSUFFICIENT_BUFFER … #define STATUS_UNAUTHORIZED_REQUEST … #define STATUS_FLASHROM_SAVE_FAILED … #define STATUS_FLASHROM_RESTORE_FAILED … #define STATUS_ICCBINDEX_ALLOC_FAILED … #define STATUS_IOCTLHANDLE_ALLOC_FAILED … #define STATUS_INVALID_PHY_ADDR_FROM_OSM … #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM … #define STATUS_ASSERT_FAILED … #define STATUS_INVALID_SESSION … #define STATUS_INVALID_CONNECTION … #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT … #define STATUS_BTL_NO_FREE_SLOT_PATH … #define STATUS_BTL_NO_FREE_SLOT_TGTID … #define STATUS_OSM_DEVSLOT_NOT_FOUND … #define STATUS_FLASHROM_READ_FAILED … #define STATUS_POLL_IOCTL_TIMEOUT … #define STATUS_ERROR_ACITMAIN … #define STATUS_REBOOT_REQUIRED … #define STATUS_FCF_IN_USE … #define STATUS_FCF_TABLE_EMPTY … /* * Additional status field for embedded SLI_CONFIG mailbox * command. */ #define ADD_STATUS_OPERATION_ALREADY_ACTIVE … #define ADD_STATUS_FW_NOT_SUPPORTED … #define ADD_STATUS_INVALID_REQUEST … #define ADD_STATUS_INVALID_OBJECT_NAME … #define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED … struct lpfc_mbx_sli4_config { … }; struct lpfc_mbx_init_vfi { … }; #define MBX_VFI_IN_USE … struct lpfc_mbx_reg_vfi { … }; struct lpfc_mbx_init_vpi { … }; struct lpfc_mbx_read_vpi { … }; struct lpfc_mbx_unreg_vfi { … }; struct lpfc_mbx_resume_rpi { … }; #define REG_FCF_INVALID_QID … struct lpfc_mbx_reg_fcfi { … }; struct lpfc_mbx_reg_fcfi_mrq { … }; struct lpfc_mbx_unreg_fcfi { … }; struct lpfc_mbx_read_rev { … }; struct lpfc_mbx_read_config { … }; struct lpfc_mbx_request_features { … }; struct lpfc_mbx_memory_dump_type3 { … }; #define DMP_PAGE_A0 … #define DMP_PAGE_A2 … #define DMP_SFF_PAGE_A0_SIZE … #define DMP_SFF_PAGE_A2_SIZE … #define SFP_WAVELENGTH_LC1310 … #define SFP_WAVELENGTH_LL1550 … /* * * SFF-8472 TABLE 3.4 * */ #define SFF_PG0_CONNECTOR_UNKNOWN … #define SFF_PG0_CONNECTOR_SC … #define SFF_PG0_CONNECTOR_FC_COPPER1 … #define SFF_PG0_CONNECTOR_FC_COPPER2 … #define SFF_PG0_CONNECTOR_BNC … #define SFF_PG0_CONNECTOR__FC_COAX … #define SFF_PG0_CONNECTOR_FIBERJACK … #define SFF_PG0_CONNECTOR_LC … #define SFF_PG0_CONNECTOR_MT … #define SFF_PG0_CONNECTOR_MU … #define SFF_PG0_CONNECTOR_SF … #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL … #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL … #define SFF_PG0_CONNECTOR_HSSDC_II … #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL … #define SFF_PG0_CONNECTOR_RJ45 … /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ #define SSF_IDENTIFIER … #define SSF_EXT_IDENTIFIER … #define SSF_CONNECTOR … #define SSF_TRANSCEIVER_CODE_B0 … #define SSF_TRANSCEIVER_CODE_B1 … #define SSF_TRANSCEIVER_CODE_B2 … #define SSF_TRANSCEIVER_CODE_B3 … #define SSF_TRANSCEIVER_CODE_B4 … #define SSF_TRANSCEIVER_CODE_B5 … #define SSF_TRANSCEIVER_CODE_B6 … #define SSF_TRANSCEIVER_CODE_B7 … #define SSF_ENCODING … #define SSF_BR_NOMINAL … #define SSF_RATE_IDENTIFIER … #define SSF_LENGTH_9UM_KM … #define SSF_LENGTH_9UM … #define SSF_LENGTH_50UM_OM2 … #define SSF_LENGTH_62UM_OM1 … #define SFF_LENGTH_COPPER … #define SSF_LENGTH_50UM_OM3 … #define SSF_VENDOR_NAME … #define SSF_TRANSCEIVER2 … #define SSF_VENDOR_OUI … #define SSF_VENDOR_PN … #define SSF_VENDOR_REV … #define SSF_WAVELENGTH_B1 … #define SSF_WAVELENGTH_B0 … #define SSF_CC_BASE … #define SSF_OPTIONS_B1 … #define SSF_OPTIONS_B0 … #define SSF_BR_MAX … #define SSF_BR_MIN … #define SSF_VENDOR_SN … #define SSF_DATE_CODE … #define SSF_MONITORING_TYPEDIAGNOSTIC … #define SSF_ENHANCED_OPTIONS … #define SFF_8472_COMPLIANCE … #define SSF_CC_EXT … #define SSF_A0_VENDOR_SPECIFIC … /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ #define SSF_TEMP_HIGH_ALARM … #define SSF_TEMP_LOW_ALARM … #define SSF_TEMP_HIGH_WARNING … #define SSF_TEMP_LOW_WARNING … #define SSF_VOLTAGE_HIGH_ALARM … #define SSF_VOLTAGE_LOW_ALARM … #define SSF_VOLTAGE_HIGH_WARNING … #define SSF_VOLTAGE_LOW_WARNING … #define SSF_BIAS_HIGH_ALARM … #define SSF_BIAS_LOW_ALARM … #define SSF_BIAS_HIGH_WARNING … #define SSF_BIAS_LOW_WARNING … #define SSF_TXPOWER_HIGH_ALARM … #define SSF_TXPOWER_LOW_ALARM … #define SSF_TXPOWER_HIGH_WARNING … #define SSF_TXPOWER_LOW_WARNING … #define SSF_RXPOWER_HIGH_ALARM … #define SSF_RXPOWER_LOW_ALARM … #define SSF_RXPOWER_HIGH_WARNING … #define SSF_RXPOWER_LOW_WARNING … #define SSF_EXT_CAL_CONSTANTS … #define SSF_CC_DMI … #define SFF_TEMPERATURE_B1 … #define SFF_TEMPERATURE_B0 … #define SFF_VCC_B1 … #define SFF_VCC_B0 … #define SFF_TX_BIAS_CURRENT_B1 … #define SFF_TX_BIAS_CURRENT_B0 … #define SFF_TXPOWER_B1 … #define SFF_TXPOWER_B0 … #define SFF_RXPOWER_B1 … #define SFF_RXPOWER_B0 … #define SSF_STATUS_CONTROL … #define SSF_ALARM_FLAGS … #define SSF_WARNING_FLAGS … #define SSF_EXT_TATUS_CONTROL_B1 … #define SSF_EXT_TATUS_CONTROL_B0 … #define SSF_A2_VENDOR_SPECIFIC … #define SSF_USER_EEPROM … #define SSF_VENDOR_CONTROL … /* * Tranceiver codes Fibre Channel SFF-8472 * Table 3.5. */ struct sff_trasnceiver_codes_byte0 { … }; struct sff_trasnceiver_codes_byte1 { … }; struct sff_trasnceiver_codes_byte2 { … }; struct sff_trasnceiver_codes_byte3 { … }; struct sff_trasnceiver_codes_byte4 { … }; struct sff_trasnceiver_codes_byte5 { … }; struct sff_trasnceiver_codes_byte6 { … }; struct sff_trasnceiver_codes_byte7 { … }; /* User writable non-volatile memory, SFF-8472 Table 3.20 */ struct user_eeprom { … }; #define SLI4_PAGE_ALIGN(addr) … struct lpfc_sli4_parameters { … }; #define LPFC_SET_UE_RECOVERY … #define LPFC_SET_MDS_DIAGS … #define LPFC_SET_DUAL_DUMP … #define LPFC_SET_CGN_SIGNAL … #define LPFC_SET_ENABLE_MI … #define LPFC_SET_LD_SIGNAL … #define LPFC_SET_ENABLE_CMF … struct lpfc_mbx_set_feature { … }; #define LPFC_SET_HOST_OS_DRIVER_VERSION … #define LPFC_SET_HOST_DATE_TIME … struct lpfc_mbx_set_host_date_time { … }; struct lpfc_mbx_set_host_data { … }; struct lpfc_mbx_set_trunk_mode { … }; struct lpfc_mbx_get_sli4_parameters { … }; struct lpfc_mbx_reg_congestion_buf { … }; struct lpfc_rscr_desc_generic { … }; struct lpfc_rsrc_desc_pcie { … }; struct lpfc_rsrc_desc_fcfcoe { … }; struct lpfc_func_cfg { … }; struct lpfc_mbx_get_func_cfg { … }; struct lpfc_prof_cfg { … }; struct lpfc_mbx_get_prof_cfg { … }; struct lpfc_controller_attribute { … }; struct lpfc_mbx_get_cntl_attributes { … }; struct lpfc_mbx_get_port_name { … }; /* Mailbox Completion Queue Error Messages */ #define MB_CQE_STATUS_SUCCESS … #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES … #define MB_CQE_STATUS_INVALID_PARAMETER … #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES … #define MB_CEQ_STATUS_QUEUE_FLUSHING … #define MB_CQE_STATUS_DMA_FAILED … #define LPFC_MBX_WR_CONFIG_MAX_BDE … struct lpfc_mbx_wr_object { … }; /* mailbox queue entry structure */ struct lpfc_mqe { … }; struct lpfc_mcqe { … }; struct lpfc_acqe_link { … }; struct lpfc_acqe_fip { … }; struct lpfc_acqe_dcbx { … }; struct lpfc_acqe_grp5 { … }; extern const char *const trunk_errmsg[]; struct lpfc_acqe_fc_la { … }; struct lpfc_acqe_misconfigured_event { … }; struct lpfc_acqe_cgn_signal { … }; struct lpfc_acqe_sli { … }; /* * Define the bootstrap mailbox (bmbx) region used to communicate * mailbox command between the host and port. The mailbox consists * of a payload area of 256 bytes and a completion queue of length * 16 bytes. */ struct lpfc_bmbx_create { … }; #define SGL_ALIGN_SZ … #define SGL_PAGE_SIZE … /* align SGL addr on a size boundary - adjust address up */ #define NO_XRI … struct wqe_common { … }; struct wqe_did { … }; struct lpfc_wqe_generic{ … }; enum els_request64_wqe_word11 { … }; struct els_request64_wqe { … }; struct xmit_els_rsp64_wqe { … }; struct xmit_bls_rsp64_wqe { … }; struct wqe_rctl_dfctl { … }; struct xmit_seq64_wqe { … }; struct xmit_bcast64_wqe { … }; struct gen_req64_wqe { … }; /* Define NVME PRLI request to fabric. NVME is a * fabric-only protocol. * Updated to red-lined v1.08 on Sept 16, 2016 */ struct lpfc_nvme_prli { … }; struct create_xri_wqe { … }; #define T_REQUEST_TAG … #define T_XRI_TAG … struct cmf_sync_wqe { … }; struct abort_cmd_wqe { … }; struct fcp_iwrite64_wqe { … }; struct fcp_iread64_wqe { … }; struct fcp_icmnd64_wqe { … }; struct fcp_trsp64_wqe { … }; struct fcp_tsend64_wqe { … }; struct fcp_treceive64_wqe { … }; #define TXRDY_PAYLOAD_LEN … #define CMD_SEND_FRAME … struct send_frame_wqe { … }; #define ELS_RDF_REG_TAG_CNT … struct lpfc_els_rdf_reg_desc { … }; struct lpfc_els_rdf_req { … }; struct lpfc_els_rdf_rsp { … }; lpfc_wqe; lpfc_wqe128; #define MAGIC_NUMBER_G6 … #define MAGIC_NUMBER_G7 … #define MAGIC_NUMBER_G7P … struct lpfc_grp_hdr { … }; /* Defines for WQE command type */ #define FCP_COMMAND … #define NVME_READ_CMD … #define FCP_COMMAND_DATA_OUT … #define NVME_WRITE_CMD … #define COMMAND_DATA_IN … #define COMMAND_DATA_OUT … #define FCP_COMMAND_TRECEIVE … #define FCP_COMMAND_TRSP … #define FCP_COMMAND_TSEND … #define OTHER_COMMAND … #define CMF_SYNC_COMMAND … #define ELS_COMMAND_NON_FIP … #define ELS_COMMAND_FIP … #define LPFC_NVME_EMBED_CMD … #define LPFC_NVME_EMBED_WRITE … #define LPFC_NVME_EMBED_READ … /* WQE Commands */ #define CMD_ABORT_XRI_WQE … #define CMD_XMIT_SEQUENCE64_WQE … #define CMD_XMIT_BCAST64_WQE … #define CMD_ELS_REQUEST64_WQE … #define CMD_XMIT_ELS_RSP64_WQE … #define CMD_XMIT_BLS_RSP64_WQE … #define CMD_FCP_IWRITE64_WQE … #define CMD_FCP_IREAD64_WQE … #define CMD_FCP_ICMND64_WQE … #define CMD_FCP_TSEND64_WQE … #define CMD_FCP_TRECEIVE64_WQE … #define CMD_FCP_TRSP64_WQE … #define CMD_GEN_REQUEST64_WQE … #define CMD_CMF_SYNC_WQE … #define CMD_WQE_MASK … #define LPFC_FW_DUMP … #define LPFC_FW_RESET … #define LPFC_DV_RESET … /* On some kernels, enum fc_ls_tlv_dtag does not have * these 2 enums defined, on other kernels it does. * To get aound this we need to add these 2 defines here. */ #ifndef ELS_DTAG_LNK_FAULT_CAP #define ELS_DTAG_LNK_FAULT_CAP … #endif #ifndef ELS_DTAG_CG_SIGNAL_CAP #define ELS_DTAG_CG_SIGNAL_CAP … #endif /* * Initializer useful for decoding FPIN string table. */ #define FC_FPIN_CONGN_SEVERITY_INIT … /* Used for logging FPIN messages */ #define LPFC_FPIN_WWPN_LINE_SZ … #define LPFC_FPIN_WWPN_LINE_CNT … #define LPFC_FPIN_WWPN_NUM_LINE …
Codebase Browser
linux