/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. * Copyright (c) 2014- QLogic Corporation. * All rights reserved * www.qlogic.com * * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter. */ /* * bfi_reg.h ASIC register defines for all QLogic BR-series adapter ASICs */ #ifndef __BFI_REG_H__ #define __BFI_REG_H__ #define HOSTFN0_INT_STATUS … #define HOSTFN1_INT_STATUS … #define HOSTFN2_INT_STATUS … #define HOSTFN3_INT_STATUS … #define HOSTFN0_INT_MSK … #define HOSTFN1_INT_MSK … #define HOSTFN2_INT_MSK … #define HOSTFN3_INT_MSK … #define HOST_PAGE_NUM_FN0 … #define HOST_PAGE_NUM_FN1 … #define HOST_PAGE_NUM_FN2 … #define HOST_PAGE_NUM_FN3 … #define APP_PLL_LCLK_CTL_REG … #define __P_LCLK_PLL_LOCK … #define __APP_PLL_LCLK_SRAM_USE_100MHZ … #define __APP_PLL_LCLK_RESET_TIMER_MK … #define __APP_PLL_LCLK_RESET_TIMER_SH … #define __APP_PLL_LCLK_RESET_TIMER(_v) … #define __APP_PLL_LCLK_LOGIC_SOFT_RESET … #define __APP_PLL_LCLK_CNTLMT0_1_MK … #define __APP_PLL_LCLK_CNTLMT0_1_SH … #define __APP_PLL_LCLK_CNTLMT0_1(_v) … #define __APP_PLL_LCLK_JITLMT0_1_MK … #define __APP_PLL_LCLK_JITLMT0_1_SH … #define __APP_PLL_LCLK_JITLMT0_1(_v) … #define __APP_PLL_LCLK_HREF … #define __APP_PLL_LCLK_HDIV … #define __APP_PLL_LCLK_P0_1_MK … #define __APP_PLL_LCLK_P0_1_SH … #define __APP_PLL_LCLK_P0_1(_v) … #define __APP_PLL_LCLK_Z0_2_MK … #define __APP_PLL_LCLK_Z0_2_SH … #define __APP_PLL_LCLK_Z0_2(_v) … #define __APP_PLL_LCLK_RSEL200500 … #define __APP_PLL_LCLK_ENARST … #define __APP_PLL_LCLK_BYPASS … #define __APP_PLL_LCLK_LRESETN … #define __APP_PLL_LCLK_ENABLE … #define APP_PLL_SCLK_CTL_REG … #define __P_SCLK_PLL_LOCK … #define __APP_PLL_SCLK_RESET_TIMER_MK … #define __APP_PLL_SCLK_RESET_TIMER_SH … #define __APP_PLL_SCLK_RESET_TIMER(_v) … #define __APP_PLL_SCLK_LOGIC_SOFT_RESET … #define __APP_PLL_SCLK_CNTLMT0_1_MK … #define __APP_PLL_SCLK_CNTLMT0_1_SH … #define __APP_PLL_SCLK_CNTLMT0_1(_v) … #define __APP_PLL_SCLK_JITLMT0_1_MK … #define __APP_PLL_SCLK_JITLMT0_1_SH … #define __APP_PLL_SCLK_JITLMT0_1(_v) … #define __APP_PLL_SCLK_HREF … #define __APP_PLL_SCLK_HDIV … #define __APP_PLL_SCLK_P0_1_MK … #define __APP_PLL_SCLK_P0_1_SH … #define __APP_PLL_SCLK_P0_1(_v) … #define __APP_PLL_SCLK_Z0_2_MK … #define __APP_PLL_SCLK_Z0_2_SH … #define __APP_PLL_SCLK_Z0_2(_v) … #define __APP_PLL_SCLK_RSEL200500 … #define __APP_PLL_SCLK_ENARST … #define __APP_PLL_SCLK_BYPASS … #define __APP_PLL_SCLK_LRESETN … #define __APP_PLL_SCLK_ENABLE … #define __ENABLE_MAC_AHB_1 … #define __ENABLE_MAC_AHB_0 … #define __ENABLE_MAC_1 … #define __ENABLE_MAC_0 … #define HOST_SEM0_REG … #define HOST_SEM1_REG … #define HOST_SEM2_REG … #define HOST_SEM3_REG … #define HOST_SEM4_REG … #define HOST_SEM5_REG … #define HOST_SEM6_REG … #define HOST_SEM7_REG … #define HOST_SEM0_INFO_REG … #define HOST_SEM1_INFO_REG … #define HOST_SEM2_INFO_REG … #define HOST_SEM3_INFO_REG … #define HOST_SEM4_INFO_REG … #define HOST_SEM5_INFO_REG … #define HOST_SEM6_INFO_REG … #define HOST_SEM7_INFO_REG … #define HOSTFN0_LPU0_CMD_STAT … #define HOSTFN0_LPU1_CMD_STAT … #define HOSTFN1_LPU0_CMD_STAT … #define HOSTFN1_LPU1_CMD_STAT … #define HOSTFN2_LPU0_CMD_STAT … #define HOSTFN2_LPU1_CMD_STAT … #define HOSTFN3_LPU0_CMD_STAT … #define HOSTFN3_LPU1_CMD_STAT … #define LPU0_HOSTFN0_CMD_STAT … #define LPU1_HOSTFN0_CMD_STAT … #define LPU0_HOSTFN1_CMD_STAT … #define LPU1_HOSTFN1_CMD_STAT … #define LPU0_HOSTFN2_CMD_STAT … #define LPU1_HOSTFN2_CMD_STAT … #define LPU0_HOSTFN3_CMD_STAT … #define LPU1_HOSTFN3_CMD_STAT … #define PSS_CTL_REG … #define __PSS_I2C_CLK_DIV_MK … #define __PSS_I2C_CLK_DIV_SH … #define __PSS_I2C_CLK_DIV(_v) … #define __PSS_LMEM_INIT_DONE … #define __PSS_LMEM_RESET … #define __PSS_LMEM_INIT_EN … #define __PSS_LPU1_RESET … #define __PSS_LPU0_RESET … #define PSS_ERR_STATUS_REG … #define ERR_SET_REG … #define PSS_GPIO_OUT_REG … #define __PSS_GPIO_OUT_REG … #define PSS_GPIO_OE_REG … #define __PSS_GPIO_OE_REG … #define HOSTFN0_LPU_MBOX0_0 … #define HOSTFN1_LPU_MBOX0_8 … #define LPU_HOSTFN0_MBOX0_0 … #define LPU_HOSTFN1_MBOX0_8 … #define HOSTFN2_LPU_MBOX0_0 … #define HOSTFN3_LPU_MBOX0_8 … #define LPU_HOSTFN2_MBOX0_0 … #define LPU_HOSTFN3_MBOX0_8 … #define HOST_MSIX_ERR_INDEX_FN0 … #define HOST_MSIX_ERR_INDEX_FN1 … #define HOST_MSIX_ERR_INDEX_FN2 … #define HOST_MSIX_ERR_INDEX_FN3 … #define MBIST_CTL_REG … #define __EDRAM_BISTR_START … #define MBIST_STAT_REG … #define ETH_MAC_SER_REG … #define __APP_EMS_CKBUFAMPIN … #define __APP_EMS_REFCLKSEL … #define __APP_EMS_CMLCKSEL … #define __APP_EMS_REFCKBUFEN2 … #define __APP_EMS_REFCKBUFEN1 … #define __APP_EMS_CHANNEL_SEL … #define FNC_PERS_REG … #define __F3_FUNCTION_ACTIVE … #define __F3_FUNCTION_MODE … #define __F3_PORT_MAP_MK … #define __F3_PORT_MAP_SH … #define __F3_PORT_MAP(_v) … #define __F3_VM_MODE … #define __F3_INTX_STATUS_MK … #define __F3_INTX_STATUS_SH … #define __F3_INTX_STATUS(_v) … #define __F2_FUNCTION_ACTIVE … #define __F2_FUNCTION_MODE … #define __F2_PORT_MAP_MK … #define __F2_PORT_MAP_SH … #define __F2_PORT_MAP(_v) … #define __F2_VM_MODE … #define __F2_INTX_STATUS_MK … #define __F2_INTX_STATUS_SH … #define __F2_INTX_STATUS(_v) … #define __F1_FUNCTION_ACTIVE … #define __F1_FUNCTION_MODE … #define __F1_PORT_MAP_MK … #define __F1_PORT_MAP_SH … #define __F1_PORT_MAP(_v) … #define __F1_VM_MODE … #define __F1_INTX_STATUS_MK … #define __F1_INTX_STATUS_SH … #define __F1_INTX_STATUS(_v) … #define __F0_FUNCTION_ACTIVE … #define __F0_FUNCTION_MODE … #define __F0_PORT_MAP_MK … #define __F0_PORT_MAP_SH … #define __F0_PORT_MAP(_v) … #define __F0_VM_MODE … #define __F0_INTX_STATUS … enum { … }; #define OP_MODE … #define __APP_ETH_CLK_LOWSPEED … #define __GLOBAL_CORECLK_HALFSPEED … #define __GLOBAL_FCOE_MODE … #define FW_INIT_HALT_P0 … #define __FW_INIT_HALT_P … #define FW_INIT_HALT_P1 … #define PMM_1T_RESET_REG_P0 … #define __PMM_1T_RESET_P … #define PMM_1T_RESET_REG_P1 … /** * Catapult-2 specific defines */ #define CT2_PCI_CPQ_BASE … #define CT2_PCI_APP_BASE … #define CT2_PCI_ETH_BASE … /* * APP block registers */ #define CT2_HOSTFN_INT_STATUS … #define CT2_HOSTFN_INTR_MASK … #define CT2_HOSTFN_PERSONALITY0 … #define __PME_STATUS_ … #define __PF_VF_BAR_SIZE_MODE__MK … #define __PF_VF_BAR_SIZE_MODE__SH … #define __PF_VF_BAR_SIZE_MODE_(_v) … #define __FC_LL_PORT_MAP__MK … #define __FC_LL_PORT_MAP__SH … #define __FC_LL_PORT_MAP_(_v) … #define __PF_VF_ACTIVE_ … #define __PF_VF_CFG_RDY_ … #define __PF_VF_ENABLE_ … #define __PF_DRIVER_ACTIVE_ … #define __PF_PME_SEND_ENABLE_ … #define __PF_EXROM_OFFSET__MK … #define __PF_EXROM_OFFSET__SH … #define __PF_EXROM_OFFSET_(_v) … #define __FC_LL_MODE_ … #define __PF_INTX_PIN_ … #define CT2_HOSTFN_PERSONALITY1 … #define __PF_NUM_QUEUES1__MK … #define __PF_NUM_QUEUES1__SH … #define __PF_NUM_QUEUES1_(_v) … #define __PF_VF_QUE_OFFSET1__MK … #define __PF_VF_QUE_OFFSET1__SH … #define __PF_VF_QUE_OFFSET1_(_v) … #define __PF_VF_NUM_QUEUES__MK … #define __PF_VF_NUM_QUEUES__SH … #define __PF_VF_NUM_QUEUES_(_v) … #define __PF_VF_QUE_OFFSET_ … #define CT2_HOSTFN_PAGE_NUM … #define CT2_HOSTFN_MSIX_VT_INDEX_MBOX_ERR … /* * Catapult-2 CPQ block registers */ #define CT2_HOSTFN_LPU0_MBOX0 … #define CT2_HOSTFN_LPU1_MBOX0 … #define CT2_LPU0_HOSTFN_MBOX0 … #define CT2_LPU1_HOSTFN_MBOX0 … #define CT2_HOSTFN_LPU0_CMD_STAT … #define CT2_HOSTFN_LPU1_CMD_STAT … #define CT2_LPU0_HOSTFN_CMD_STAT … #define CT2_LPU1_HOSTFN_CMD_STAT … #define CT2_HOSTFN_LPU0_READ_STAT … #define CT2_HOSTFN_LPU1_READ_STAT … #define CT2_LPU0_HOSTFN_MBOX0_MSK … #define CT2_LPU1_HOSTFN_MBOX0_MSK … #define CT2_HOST_SEM0_REG … #define CT2_HOST_SEM1_REG … #define CT2_HOST_SEM2_REG … #define CT2_HOST_SEM3_REG … #define CT2_HOST_SEM4_REG … #define CT2_HOST_SEM5_REG … #define CT2_HOST_SEM6_REG … #define CT2_HOST_SEM7_REG … #define CT2_HOST_SEM0_INFO_REG … #define CT2_HOST_SEM1_INFO_REG … #define CT2_HOST_SEM2_INFO_REG … #define CT2_HOST_SEM3_INFO_REG … #define CT2_HOST_SEM4_INFO_REG … #define CT2_HOST_SEM5_INFO_REG … #define CT2_HOST_SEM6_INFO_REG … #define CT2_HOST_SEM7_INFO_REG … #define CT2_APP_PLL_LCLK_CTL_REG … #define __APP_LPUCLK_HALFSPEED … #define __APP_PLL_LCLK_LOAD … #define __APP_PLL_LCLK_FBCNT_MK … #define __APP_PLL_LCLK_FBCNT_SH … #define __APP_PLL_LCLK_FBCNT(_v) … enum { … }; #define __APP_PLL_LCLK_EXTFB … #define __APP_PLL_LCLK_ENOUTS … #define __APP_PLL_LCLK_RATE … #define CT2_APP_PLL_SCLK_CTL_REG … #define __P_SCLK_PLL_LOCK … #define __APP_PLL_SCLK_REFCLK_SEL … #define __APP_PLL_SCLK_CLK_DIV2 … #define __APP_PLL_SCLK_LOAD … #define __APP_PLL_SCLK_FBCNT_MK … #define __APP_PLL_SCLK_FBCNT_SH … #define __APP_PLL_SCLK_FBCNT(_v) … enum { … }; #define __APP_PLL_SCLK_EXTFB … #define __APP_PLL_SCLK_ENOUTS … #define __APP_PLL_SCLK_RATE … #define CT2_PCIE_MISC_REG … #define __ETH_CLK_ENABLE_PORT1 … #define CT2_CHIP_MISC_PRG … #define __ETH_CLK_ENABLE_PORT0 … #define __APP_LPU_SPEED … #define CT2_MBIST_STAT_REG … #define CT2_MBIST_CTL_REG … #define CT2_PMM_1T_CONTROL_REG_P0 … #define __PMM_1T_PNDB_P … #define CT2_PMM_1T_CONTROL_REG_P1 … #define CT2_WGN_STATUS … #define __A2T_AHB_LOAD … #define __WGN_READY … #define __GLBL_PF_VF_CFG_RDY … #define CT2_NFC_STS_REG … #define CT2_NFC_CSR_CLR_REG … #define CT2_NFC_CSR_SET_REG … #define __HALT_NFC_CONTROLLER … #define __NFC_CONTROLLER_HALTED … #define CT2_RSC_GPR15_REG … #define CT2_CSI_FW_CTL_REG … #define CT2_CSI_FW_CTL_SET_REG … #define __RESET_AND_START_SCLK_LCLK_PLLS … #define CT2_CSI_MAC0_CONTROL_REG … #define __CSI_MAC_RESET … #define __CSI_MAC_AHB_RESET … #define CT2_CSI_MAC1_CONTROL_REG … #define CT2_CSI_MAC_CONTROL_REG(__n) … #define CT2_NFC_FLASH_STS_REG … #define __FLASH_PLL_INIT_AND_RESET_IN_PROGRESS … /* * Name semaphore registers based on usage */ #define BFA_IOC0_HBEAT_REG … #define BFA_IOC0_STATE_REG … #define BFA_IOC1_HBEAT_REG … #define BFA_IOC1_STATE_REG … #define BFA_FW_USE_COUNT … #define BFA_IOC_FAIL_SYNC … /* * CT2 semaphore register locations changed */ #define CT2_BFA_IOC0_HBEAT_REG … #define CT2_BFA_IOC0_STATE_REG … #define CT2_BFA_IOC1_HBEAT_REG … #define CT2_BFA_IOC1_STATE_REG … #define CT2_BFA_FW_USE_COUNT … #define CT2_BFA_IOC_FAIL_SYNC … #define CPE_Q_NUM(__fn, __q) … #define RME_Q_NUM(__fn, __q) … /* * And corresponding host interrupt status bit field defines */ #define __HFN_INT_CPE_Q0 … #define __HFN_INT_CPE_Q1 … #define __HFN_INT_CPE_Q2 … #define __HFN_INT_CPE_Q3 … #define __HFN_INT_CPE_Q4 … #define __HFN_INT_CPE_Q5 … #define __HFN_INT_CPE_Q6 … #define __HFN_INT_CPE_Q7 … #define __HFN_INT_RME_Q0 … #define __HFN_INT_RME_Q1 … #define __HFN_INT_RME_Q2 … #define __HFN_INT_RME_Q3 … #define __HFN_INT_RME_Q4 … #define __HFN_INT_RME_Q5 … #define __HFN_INT_RME_Q6 … #define __HFN_INT_RME_Q7 … #define __HFN_INT_ERR_EMC … #define __HFN_INT_ERR_LPU0 … #define __HFN_INT_ERR_LPU1 … #define __HFN_INT_ERR_PSS … #define __HFN_INT_MBOX_LPU0 … #define __HFN_INT_MBOX_LPU1 … #define __HFN_INT_MBOX1_LPU0 … #define __HFN_INT_MBOX1_LPU1 … #define __HFN_INT_LL_HALT … #define __HFN_INT_CPE_MASK … #define __HFN_INT_RME_MASK … #define __HFN_INT_ERR_MASK … #define __HFN_INT_FN0_MASK … #define __HFN_INT_FN1_MASK … /* * Host interrupt status defines for catapult-2 */ #define __HFN_INT_MBOX_LPU0_CT2 … #define __HFN_INT_MBOX_LPU1_CT2 … #define __HFN_INT_ERR_PSS_CT2 … #define __HFN_INT_ERR_LPU0_CT2 … #define __HFN_INT_ERR_LPU1_CT2 … #define __HFN_INT_CPQ_HALT_CT2 … #define __HFN_INT_ERR_WGN_CT2 … #define __HFN_INT_ERR_LEHRX_CT2 … #define __HFN_INT_ERR_LEHTX_CT2 … #define __HFN_INT_ERR_MASK_CT2 … #define __HFN_INT_FN0_MASK_CT2 … #define __HFN_INT_FN1_MASK_CT2 … /* * asic memory map. */ #define PSS_SMEM_PAGE_START … #define PSS_SMEM_PGNUM(_pg0, _ma) … #define PSS_SMEM_PGOFF(_ma) … #endif /* __BFI_REG_H__ */
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