/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright 2000-2020 Broadcom Inc. All rights reserved. * * * Name: mpi2_cnfg.h * Title: MPI Configuration messages and pages * Creation Date: November 10, 2006 * * mpi2_cnfg.h Version: 02.00.47 * * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 * prefix are for use only on MPI v2.5 products, and must not be used * with MPI v2.0 products. Unless otherwise noted, names beginning with * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. * * Version History * --------------- * * Date Version Description * -------- -------- ------------------------------------------------------ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. * Added Manufacturing Page 11. * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE * define. * 06-26-07 02.00.02 Adding generic structure for product-specific * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. * Rework of BIOS Page 2 configuration page. * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the * forms. * Added configuration pages IOC Page 8 and Driver * Persistent Mapping Page 0. * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, * RAID Physical Disk Pages 0 and 1, RAID Configuration * Page 0). * Added new value for AccessStatus field of SAS Device * Page 0 (_SATA_NEEDS_INITIALIZATION). * 10-31-07 02.00.04 Added missing SEPDevHandle field to * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for * NVDATA. * Modified IOC Page 7 to use masks and added field for * SASBroadcastPrimitiveMasks. * Added MPI2_CONFIG_PAGE_BIOS_4. * Added MPI2_CONFIG_PAGE_LOG_0. * 02-29-08 02.00.06 Modified various names to make them 32-character unique. * Added SAS Device IDs. * Updated Integrated RAID configuration pages including * Manufacturing Page 4, IOC Page 6, and RAID Configuration * Page 0. * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. * Added missing MaxNumRoutedSasAddresses field to * MPI2_CONFIG_PAGE_EXPANDER_0. * Added SAS Port Page 0. * Modified structure layout for * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF * to 0x000000FF. * Added two new values for the Physical Disk Coercion Size * bits in the Flags field of Manufacturing Page 4. * Added product-specific Manufacturing pages 16 to 31. * Modified Flags bits for controlling write cache on SATA * drives in IO Unit Page 1. * Added new bit to AdditionalControlFlags of SAS IO Unit * Page 1 to control Invalid Topology Correction. * Added additional defines for RAID Volume Page 0 * VolumeStatusFlags field. * Modified meaning of RAID Volume Page 0 VolumeSettings * define for auto-configure of hot-swap drives. * Added SupportedPhysDisks field to RAID Volume Page 1 and * added related defines. * Added PhysDiskAttributes field (and related defines) to * RAID Physical Disk Page 0. * Added MPI2_SAS_PHYINFO_PHY_VACANT define. * Added three new DiscoveryStatus bits for SAS IO Unit * Page 0 and SAS Expander Page 0. * Removed multiplexing information from SAS IO Unit pages. * Added BootDeviceWaitTime field to SAS IO Unit Page 4. * Removed Zone Address Resolved bit from PhyInfo and from * Expander Page 0 Flags field. * Added two new AccessStatus values to SAS Device Page 0 * for indicating routing problems. Added 3 reserved words * to this page. * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. * Inserted missing reserved field into structure for IOC * Page 6. * Added more pending task bits to RAID Volume Page 0 * VolumeStatusFlags defines. * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 * and SAS Expander Page 0 to flag a downstream initiator * when in simplified routing mode. * Removed SATA Init Failure defines for DiscoveryStatus * fields of SAS IO Unit Page 0 and SAS Expander Page 0. * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. * Added PortGroups, DmaGroup, and ControlGroup fields to * SAS Device Page 0. * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO * Unit Page 6. * Added expander reduced functionality data to SAS * Expander Page 0. * Added SAS PHY Page 2 and SAS PHY Page 3. * 07-30-09 02.00.12 Added IO Unit Page 7. * Added new device ids. * Added SAS IO Unit Page 5. * Added partial and slumber power management capable flags * to SAS Device Page 0 Flags field. * Added PhyInfo defines for power condition. * Added Ethernet configuration pages. * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. * Added SAS PHY Page 4 structure and defines. * 02-10-10 02.00.14 Modified the comments for the configuration page * structures that contain an array of data. The host * should use the "count" field in the page data (e.g. the * NumPhys field) to determine the number of valid elements * in the array. * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. * Added PowerManagementCapabilities to IO Unit Page 7. * Added PortWidthModGroup field to * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT * define. * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) * defines. * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for * the Pinout field. * Added BoardTemperature and BoardTemperatureUnits fields * to MPI2_CONFIG_PAGE_IO_UNIT_7. * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. * Added IO Unit Page 8, IO Unit Page 9, * and IO Unit Page 10. * Added SASNotifyPrimitiveMasks field to * MPI2_CONFIG_PAGE_IOC_7. * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). * 05-25-11 02.00.20 Cleaned up a few comments. * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities * for PCIe link as obsolete. * Added SpinupFlags field containing a Disable Spin-up bit * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO * Unit Page 4. * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. * Added UEFIVersion field to BIOS Page 1 and defined new * BiosOptions bits. * Incorporating additions for MPI v2.5. * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as * obsolete for MPI v2.5 and later. * Added some defines for 12G SAS speeds. * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to * match the specification. * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for * future use. * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for * MPI2_CONFIG_PAGE_MAN_7. * Added EnclosureLevel and ConnectorName fields to * MPI2_CONFIG_PAGE_SAS_DEV_0. * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for * MPI2_CONFIG_PAGE_SAS_DEV_0. * Added EnclosureLevel field to * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. * 01-08-14 02.00.28 Added more defines for the BiosOptions field of * MPI2_CONFIG_PAGE_BIOS_1. * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and * more defines for the BiosOptions field. * 11-18-14 02.00.30 Updated copyright information. * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. * Added AdapterOrderAux fields to BIOS Page 3. * 03-16-15 02.00.31 Updated for MPI v2.6. * Added Flags field to IO Unit Page 7. * Added new SAS Phy Event codes * 05-25-15 02.00.33 Added more defines for the BiosOptions field of * MPI2_CONFIG_PAGE_BIOS_1. * 08-25-15 02.00.34 Bumped Header Version. * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines. * Added Link field to PCIe Link Pages * Added EnclosureLevel and ConnectorName to PCIe * Device Page 0. * Added define for PCIE IoUnit page 1 max rate shift. * Added comment for reserved ExtPageTypes. * Added SAS 4 22.5 gbs speed support. * Added PCIe 4 16.0 GT/sec speec support. * Removed AHCI support. * Removed SOP support. * Added NegotiatedLinkRate and NegotiatedPortWidth to * PCIe device page 0. * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types. * Changed declaration of ConnectorName in PCIe DevicePage0 * to match SAS DevicePage 0. * Added SATADeviceWaitTime to IO Unit Page 11. * Added MPI26_MFGPAGE_DEVID_SAS4008 * Added x16 PCIe width to IO Unit Page 7 * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1 * phy data. * Added InitStatus to PCIe IO Unit Page 1 header. * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines. * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats. * 02-02-17 02.00.40 Added MPI2_MANPAGE7_SLOT_UNKNOWN. * Added ChassisSlot field to SAS Enclosure Page 0. * Added ChassisSlot Valid bit (bit 5) to the Flags field * in SAS Enclosure Page 0. * 06-13-17 02.00.41 Added MPI26_MFGPAGE_DEVID_SAS3816 and * MPI26_MFGPAGE_DEVID_SAS3916 defines. * Removed MPI26_MFGPAGE_DEVID_SAS4008 define. * Added MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN define. * Renamed PI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS to * PI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN. * Renamed MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS to * MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK. * 09-29-17 02.00.42 Added ControllerResetTO field to PCIe Device Page 2. * Added NOIOB field to PCIe Device Page 2. * Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to * the Capabilities field of PCIe Device Page 2. * 07-22-18 02.00.43 Added defines for SAS3916 and SAS3816. * Added WRiteCache defines to IO Unit Page 1. * Added MaxEnclosureLevel to BIOS Page 1. * Added OEMRD to SAS Enclosure Page 1. * Added DMDReportPCIe to PCIe IO Unit Page 1. * Added Flags field and flags for Retimers to * PCIe Switch Page 1. * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7. * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1 * 08-28-18 02.00.46 Added NVMs Write Cache flag to IOUnitPage1 * Added DMDReport Delay Time defines to * PCIeIOUnitPage1 * -------------------------------------------------------------------------- * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7. * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1 * 08-28-18 02.00.46 Added NVMs Write Cache flag to IOUnitPage1 * Added DMDReport Delay Time defines to PCIeIOUnitPage1 * 12-17-18 02.00.47 Swap locations of Slotx2 and Slotx4 in ManPage 7. * 08-01-19 02.00.49 Add MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID * Add MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT */ #ifndef MPI2_CNFG_H #define MPI2_CNFG_H /***************************************************************************** * Configuration Page Header and defines *****************************************************************************/ /*Config Page Header */ pMpi2ConfigPageHeader_t; pMpi2ConfigPageHeaderUnion; /*Extended Config Page Header */ pMpi2ConfigExtendedPageHeader_t; pMpi2ConfigPageExtendedHeaderUnion; /*PageType field values */ #define MPI2_CONFIG_PAGEATTR_READ_ONLY … #define MPI2_CONFIG_PAGEATTR_CHANGEABLE … #define MPI2_CONFIG_PAGEATTR_PERSISTENT … #define MPI2_CONFIG_PAGEATTR_MASK … #define MPI2_CONFIG_PAGETYPE_IO_UNIT … #define MPI2_CONFIG_PAGETYPE_IOC … #define MPI2_CONFIG_PAGETYPE_BIOS … #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME … #define MPI2_CONFIG_PAGETYPE_MANUFACTURING … #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK … #define MPI2_CONFIG_PAGETYPE_EXTENDED … #define MPI2_CONFIG_PAGETYPE_MASK … #define MPI2_CONFIG_TYPENUM_MASK … /*ExtPageType field values */ #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT … #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER … #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE … #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY … #define MPI2_CONFIG_EXTPAGETYPE_LOG … #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE … #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG … #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING … #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT … #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET … #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING … #define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT … #define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH … #define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE … #define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK … /***************************************************************************** * PageAddress defines *****************************************************************************/ /*RAID Volume PageAddress format */ #define MPI2_RAID_VOLUME_PGAD_FORM_MASK … #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE … #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE … #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK … /*RAID Physical Disk PageAddress format */ #define MPI2_PHYSDISK_PGAD_FORM_MASK … #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM … #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM … #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE … #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK … #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK … /*SAS Expander PageAddress format */ #define MPI2_SAS_EXPAND_PGAD_FORM_MASK … #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL … #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM … #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL … #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK … #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK … #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT … /*SAS Device PageAddress format */ #define MPI2_SAS_DEVICE_PGAD_FORM_MASK … #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE … #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE … #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK … /*SAS PHY PageAddress format */ #define MPI2_SAS_PHY_PGAD_FORM_MASK … #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER … #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX … #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK … #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK … /*SAS Port PageAddress format */ #define MPI2_SASPORT_PGAD_FORM_MASK … #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT … #define MPI2_SASPORT_PGAD_FORM_PORT_NUM … #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK … /*SAS Enclosure PageAddress format */ #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK … #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE … #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE … #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK … /*Enclosure PageAddress format */ #define MPI26_ENCLOS_PGAD_FORM_MASK … #define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE … #define MPI26_ENCLOS_PGAD_FORM_HANDLE … #define MPI26_ENCLOS_PGAD_HANDLE_MASK … /*RAID Configuration PageAddress format */ #define MPI2_RAID_PGAD_FORM_MASK … #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM … #define MPI2_RAID_PGAD_FORM_CONFIGNUM … #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG … #define MPI2_RAID_PGAD_CONFIGNUM_MASK … /*Driver Persistent Mapping PageAddress format */ #define MPI2_DPM_PGAD_FORM_MASK … #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE … #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK … #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT … #define MPI2_DPM_PGAD_START_ENTRY_MASK … /*Ethernet PageAddress format */ #define MPI2_ETHERNET_PGAD_FORM_MASK … #define MPI2_ETHERNET_PGAD_FORM_IF_NUM … #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK … /*PCIe Switch PageAddress format */ #define MPI26_PCIE_SWITCH_PGAD_FORM_MASK … #define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL … #define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM … #define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL … #define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK … #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK … #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT … /*PCIe Device PageAddress format */ #define MPI26_PCIE_DEVICE_PGAD_FORM_MASK … #define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE … #define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE … #define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK … /*PCIe Link PageAddress format */ #define MPI26_PCIE_LINK_PGAD_FORM_MASK … #define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK … #define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM … #define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK … /**************************************************************************** * Configuration messages ****************************************************************************/ /*Configuration Request Message */ pMpi2ConfigRequest_t; /*values for the Action field */ #define MPI2_CONFIG_ACTION_PAGE_HEADER … #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT … #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT … #define MPI2_CONFIG_ACTION_PAGE_DEFAULT … #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM … #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT … #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM … #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE … /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ /*Config Reply Message */ pMpi2ConfigReply_t; /***************************************************************************** * * C o n f i g u r a t i o n P a g e s * *****************************************************************************/ /**************************************************************************** * Manufacturing Config pages ****************************************************************************/ #define MPI2_MFGPAGE_VENDORID_LSI … #define MPI2_MFGPAGE_VENDORID_ATTO … /*MPI v2.0 SAS products */ #define MPI2_MFGPAGE_DEVID_SAS2004 … #define MPI2_MFGPAGE_DEVID_SAS2008 … #define MPI2_MFGPAGE_DEVID_SAS2108_1 … #define MPI2_MFGPAGE_DEVID_SAS2108_2 … #define MPI2_MFGPAGE_DEVID_SAS2108_3 … #define MPI2_MFGPAGE_DEVID_SAS2116_1 … #define MPI2_MFGPAGE_DEVID_SAS2116_2 … #define MPI2_MFGPAGE_DEVID_SSS6200 … #define MPI2_MFGPAGE_DEVID_SAS2208_1 … #define MPI2_MFGPAGE_DEVID_SAS2208_2 … #define MPI2_MFGPAGE_DEVID_SAS2208_3 … #define MPI2_MFGPAGE_DEVID_SAS2208_4 … #define MPI2_MFGPAGE_DEVID_SAS2208_5 … #define MPI2_MFGPAGE_DEVID_SAS2208_6 … #define MPI2_MFGPAGE_DEVID_SAS2308_1 … #define MPI2_MFGPAGE_DEVID_SAS2308_2 … #define MPI2_MFGPAGE_DEVID_SAS2308_3 … #define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP … #define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP_1 … /*MPI v2.5 SAS products */ #define MPI25_MFGPAGE_DEVID_SAS3004 … #define MPI25_MFGPAGE_DEVID_SAS3008 … #define MPI25_MFGPAGE_DEVID_SAS3108_1 … #define MPI25_MFGPAGE_DEVID_SAS3108_2 … #define MPI25_MFGPAGE_DEVID_SAS3108_5 … #define MPI25_MFGPAGE_DEVID_SAS3108_6 … /* MPI v2.6 SAS Products */ #define MPI26_MFGPAGE_DEVID_SAS3216 … #define MPI26_MFGPAGE_DEVID_SAS3224 … #define MPI26_MFGPAGE_DEVID_SAS3316_1 … #define MPI26_MFGPAGE_DEVID_SAS3316_2 … #define MPI26_MFGPAGE_DEVID_SAS3316_3 … #define MPI26_MFGPAGE_DEVID_SAS3316_4 … #define MPI26_MFGPAGE_DEVID_SAS3324_1 … #define MPI26_MFGPAGE_DEVID_SAS3324_2 … #define MPI26_MFGPAGE_DEVID_SAS3324_3 … #define MPI26_MFGPAGE_DEVID_SAS3324_4 … #define MPI26_MFGPAGE_DEVID_SAS3516 … #define MPI26_MFGPAGE_DEVID_SAS3516_1 … #define MPI26_MFGPAGE_DEVID_SAS3416 … #define MPI26_MFGPAGE_DEVID_SAS3508 … #define MPI26_MFGPAGE_DEVID_SAS3508_1 … #define MPI26_MFGPAGE_DEVID_SAS3408 … #define MPI26_MFGPAGE_DEVID_SAS3716 … #define MPI26_MFGPAGE_DEVID_SAS3616 … #define MPI26_MFGPAGE_DEVID_SAS3708 … #define MPI26_MFGPAGE_DEVID_SEC_MASK_3916 … #define MPI26_MFGPAGE_DEVID_INVALID0_3916 … #define MPI26_MFGPAGE_DEVID_CFG_SEC_3916 … #define MPI26_MFGPAGE_DEVID_HARD_SEC_3916 … #define MPI26_MFGPAGE_DEVID_INVALID1_3916 … #define MPI26_MFGPAGE_DEVID_SEC_MASK_3816 … #define MPI26_MFGPAGE_DEVID_INVALID0_3816 … #define MPI26_MFGPAGE_DEVID_CFG_SEC_3816 … #define MPI26_MFGPAGE_DEVID_HARD_SEC_3816 … #define MPI26_MFGPAGE_DEVID_INVALID1_3816 … /*Manufacturing Page 0 */ pMpi2ManufacturingPage0_t; #define MPI2_MANUFACTURING0_PAGEVERSION … /*Manufacturing Page 1 */ pMpi2ManufacturingPage1_t; #define MPI2_MANUFACTURING1_PAGEVERSION … pMpi2ChipRevisionId_t; /*Manufacturing Page 2 */ /* *Host code (drivers, BIOS, utilities, etc.) should check Header.PageLength at *runtime before using HwSettings[]. */ pMpi2ManufacturingPage2_t; #define MPI2_MANUFACTURING2_PAGEVERSION … /*Manufacturing Page 3 */ /* *Host code (drivers, BIOS, utilities, etc.) should check Header.PageLength at *runtime before using Info[]. */ pMpi2ManufacturingPage3_t; #define MPI2_MANUFACTURING3_PAGEVERSION … /*Manufacturing Page 4 */ pMpi2ManPage4PwrSaveSettings_t; /*defines for the PowerSaveFlags field */ #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE … #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED … #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE … #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE … pMpi2ManufacturingPage4_t; #define MPI2_MANUFACTURING4_PAGEVERSION … /*Manufacturing Page 4 Flags field */ #define MPI2_MANPAGE4_METADATA_SIZE_MASK … #define MPI2_MANPAGE4_METADATA_512MB … #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA … #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD … #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR … #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION … #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB … #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION … #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION … #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION … #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING … #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING … #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING … #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING … #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER … #define MPI2_MANPAGE4_RAID10_DISABLE … #define MPI2_MANPAGE4_RAID1E_DISABLE … #define MPI2_MANPAGE4_RAID1_DISABLE … #define MPI2_MANPAGE4_RAID0_DISABLE … #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE … #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE … #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA … /*Manufacturing Page 5 */ /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumPhys at runtime before using Phy[]. */ pMpi2Manufacturing5Entry_t; pMpi2ManufacturingPage5_t; #define MPI2_MANUFACTURING5_PAGEVERSION … /*Manufacturing Page 6 */ pMpi2ManufacturingPage6_t; #define MPI2_MANUFACTURING6_PAGEVERSION … /*Manufacturing Page 7 */ pMpi2ManPage7ConnectorInfo_t; /*defines for the Pinout field */ #define MPI2_MANPAGE7_PINOUT_LANE_MASK … #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT … #define MPI2_MANPAGE7_PINOUT_TYPE_MASK … #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN … #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE … #define MPI2_MANPAGE7_PINOUT_SFF_8482 … #define MPI2_MANPAGE7_PINOUT_SFF_8486 … #define MPI2_MANPAGE7_PINOUT_SFF_8484 … #define MPI2_MANPAGE7_PINOUT_SFF_8087 … #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I … #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I … #define MPI2_MANPAGE7_PINOUT_SFF_8470 … #define MPI2_MANPAGE7_PINOUT_SFF_8088 … #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X … #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X … #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X … #define MPI2_MANPAGE7_PINOUT_SFF_8436 … #define MPI2_MANPAGE7_PINOUT_SFF_8088_A … #define MPI2_MANPAGE7_PINOUT_SFF_8643_16i … #define MPI2_MANPAGE7_PINOUT_SFF_8654_4i … #define MPI2_MANPAGE7_PINOUT_SFF_8654_8i … #define MPI2_MANPAGE7_PINOUT_SFF_8611_4i … #define MPI2_MANPAGE7_PINOUT_SFF_8611_8i … /*defines for the Location field */ #define MPI2_MANPAGE7_LOCATION_UNKNOWN … #define MPI2_MANPAGE7_LOCATION_INTERNAL … #define MPI2_MANPAGE7_LOCATION_EXTERNAL … #define MPI2_MANPAGE7_LOCATION_SWITCHABLE … #define MPI2_MANPAGE7_LOCATION_AUTO … #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT … #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED … /*defines for the Slot field */ #define MPI2_MANPAGE7_SLOT_UNKNOWN … /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumPhys at runtime before using ConnectorInfo[]. */ pMpi2ManufacturingPage7_t; #define MPI2_MANUFACTURING7_PAGEVERSION … /*defines for the Flags field */ #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL … #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER … #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO … #define MPI26_MANPAGE7_FLAG_CONN_LANE_USE_PINOUT … #define MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID … /* *Generic structure to use for product-specific manufacturing pages *(currently Manufacturing Page 8 through Manufacturing Page 31). */ pMpi2ManufacturingPagePS_t; #define MPI2_MANUFACTURING8_PAGEVERSION … #define MPI2_MANUFACTURING9_PAGEVERSION … #define MPI2_MANUFACTURING10_PAGEVERSION … #define MPI2_MANUFACTURING11_PAGEVERSION … #define MPI2_MANUFACTURING12_PAGEVERSION … #define MPI2_MANUFACTURING13_PAGEVERSION … #define MPI2_MANUFACTURING14_PAGEVERSION … #define MPI2_MANUFACTURING15_PAGEVERSION … #define MPI2_MANUFACTURING16_PAGEVERSION … #define MPI2_MANUFACTURING17_PAGEVERSION … #define MPI2_MANUFACTURING18_PAGEVERSION … #define MPI2_MANUFACTURING19_PAGEVERSION … #define MPI2_MANUFACTURING20_PAGEVERSION … #define MPI2_MANUFACTURING21_PAGEVERSION … #define MPI2_MANUFACTURING22_PAGEVERSION … #define MPI2_MANUFACTURING23_PAGEVERSION … #define MPI2_MANUFACTURING24_PAGEVERSION … #define MPI2_MANUFACTURING25_PAGEVERSION … #define MPI2_MANUFACTURING26_PAGEVERSION … #define MPI2_MANUFACTURING27_PAGEVERSION … #define MPI2_MANUFACTURING28_PAGEVERSION … #define MPI2_MANUFACTURING29_PAGEVERSION … #define MPI2_MANUFACTURING30_PAGEVERSION … #define MPI2_MANUFACTURING31_PAGEVERSION … /**************************************************************************** * IO Unit Config Pages ****************************************************************************/ /*IO Unit Page 0 */ pMpi2IOUnitPage0_t; #define MPI2_IOUNITPAGE0_PAGEVERSION … /*IO Unit Page 1 */ pMpi2IOUnitPage1_t; #define MPI2_IOUNITPAGE1_PAGEVERSION … /* IO Unit Page 1 Flags defines */ #define MPI26_IOUNITPAGE1_NVME_WRCACHE_MASK … #define MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT … #define MPI26_IOUNITPAGE1_NVME_WRCACHE_NO_CHANGE … #define MPI26_IOUNITPAGE1_NVME_WRCACHE_ENABLE … #define MPI26_IOUNITPAGE1_NVME_WRCACHE_DISABLE … #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK … #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE … #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH … #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY … #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE … #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT … #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE … #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE … #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE … #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE … #define MPI2_IOUNITPAGE1_DISABLE_IR … #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING … #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID … /*IO Unit Page 3 */ /* *Host code (drivers, BIOS, utilities, etc.) should leave this define set to *36 and check the value returned for GPIOCount at runtime. */ #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX … #endif pMpi2IOUnitPage3_t; #define MPI2_IOUNITPAGE3_PAGEVERSION … /*defines for IO Unit Page 3 GPIOVal field */ #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK … #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT … #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF … #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON … /*IO Unit Page 5 */ /* *Upper layer code (drivers, utilities, etc.) should check the value returned *for NumDmaEngines at runtime before using DmaEngineCapabilities[]. */ pMpi2IOUnitPage5_t; #define MPI2_IOUNITPAGE5_PAGEVERSION … /*defines for IO Unit Page 5 DmaEngineCapabilities field */ #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS … #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS … #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP … #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION … #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING … #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION … /*IO Unit Page 6 */ pMpi2IOUnitPage6_t; #define MPI2_IOUNITPAGE6_PAGEVERSION … /*defines for IO Unit Page 6 Flags field */ #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR … /*IO Unit Page 7 */ pMpi2IOUnitPage7_t; #define MPI2_IOUNITPAGE7_PAGEVERSION … /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ #define MPI25_IOUNITPAGE7_PM_INIT_MASK … #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE … #define MPI25_IOUNITPAGE7_PM_INIT_HOST … #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT … #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA … #define MPI25_IOUNITPAGE7_PM_MODE_MASK … #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE … #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN … #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER … #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER … #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY … /*defines for IO Unit Page 7 PCIeWidth field */ #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 … #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 … #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 … #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 … #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 … /*defines for IO Unit Page 7 PCIeSpeed field */ #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS … #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS … #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS … #define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS … /*defines for IO Unit Page 7 ProcessorState field */ #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND … #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND … #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT … #define MPI2_IOUNITPAGE7_PSTATE_DISABLED … #define MPI2_IOUNITPAGE7_PSTATE_ENABLED … /*defines for IO Unit Page 7 PowerManagementCapabilities field */ #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE … #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE … #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE … #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE … #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE … #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE … #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE … #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE … #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE … #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED … #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED … #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED … #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED … #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED … #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED … #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE … #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE … #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE … #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE … /*obsolete names for the PowerManagementCapabilities bits (above) */ #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED … #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED … #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED … #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE … #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE … /*defines for IO Unit Page 7 IOCTemperatureUnits field */ #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT … #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT … #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS … /*defines for IO Unit Page 7 IOCSpeed field */ #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL … #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF … #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER … #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH … /*defines for IO Unit Page 7 BoardTemperatureUnits field */ #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT … #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT … #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS … /* defines for IO Unit Page 7 Flags field */ #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC … /*IO Unit Page 8 */ #define MPI2_IOUNIT8_NUM_THRESHOLDS … pMpi2IOUnit8Sensor_t; /*defines for IO Unit Page 8 Sensor Flags field */ #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE … #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE … #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE … #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE … /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumSensors at runtime before using Sensor[]. */ pMpi2IOUnitPage8_t; #define MPI2_IOUNITPAGE8_PAGEVERSION … /*IO Unit Page 9 */ pMpi2IOUnit9Sensor_t; /*defines for IO Unit Page 9 Sensor Flags field */ #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID … /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumSensors at runtime before using Sensor[]. */ pMpi2IOUnitPage9_t; #define MPI2_IOUNITPAGE9_PAGEVERSION … /*IO Unit Page 10 */ pMpi2IOUnit10Function_t; /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumFunctions at runtime before using Function[]. */ pMpi2IOUnitPage10_t; #define MPI2_IOUNITPAGE10_PAGEVERSION … /* IO Unit Page 11 (for MPI v2.6 and later) */ pMpi26IOUnit11SpinupGroup_t; /* defines for IO Unit Page 11 SpinupFlags */ #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG … /* * Host code (drivers, BIOS, utilities, etc.) should leave this define set to * four and check the value returned for NumPhys at runtime. */ #ifndef MPI26_IOUNITPAGE11_PHY_MAX #define MPI26_IOUNITPAGE11_PHY_MAX … #endif pMpi26IOUnitPage11_t; #define MPI26_IOUNITPAGE11_PAGEVERSION … /* defines for Flags field */ #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE … /* defines for PHY field */ #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK … /**************************************************************************** * IOC Config Pages ****************************************************************************/ /*IOC Page 0 */ pMpi2IOCPage0_t; #define MPI2_IOCPAGE0_PAGEVERSION … /*IOC Page 1 */ pMpi2IOCPage1_t; #define MPI2_IOCPAGE1_PAGEVERSION … /*defines for IOC Page 1 Flags field */ #define MPI2_IOCPAGE1_REPLY_COALESCING … #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN … #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN … #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN … /*IOC Page 6 */ pMpi2IOCPage6_t; #define MPI2_IOCPAGE6_PAGEVERSION … /*defines for IOC Page 6 CapabilitiesFlags */ #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT … #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT … #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT … #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT … #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT … #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE … /*IOC Page 7 */ #define MPI2_IOCPAGE7_EVENTMASK_WORDS … pMpi2IOCPage7_t; #define MPI2_IOCPAGE7_PAGEVERSION … /*IOC Page 8 */ pMpi2IOCPage8_t; #define MPI2_IOCPAGE8_PAGEVERSION … /*defines for IOC Page 8 Flags field */ #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 … #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 … #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE … #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING … #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING … #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING … #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING … /*defines for IOC Page 8 IRVolumeMappingFlags */ #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE … #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING … #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING … /**************************************************************************** * BIOS Config Pages ****************************************************************************/ /*BIOS Page 1 */ pMpi2BiosPage1_t; #define MPI2_BIOSPAGE1_PAGEVERSION … /*values for BIOS Page 1 BiosOptions field */ #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE … #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG … #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK … #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL … #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE … #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID … #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS … #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY … #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS … #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD … #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD … #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD … #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD … #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD … #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID … #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID … #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION … #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII … #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII … #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII … #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS … /*values for BIOS Page 1 IOCSettings field */ #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE … #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT … #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT … #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING … #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING … #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING … #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING … #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT … #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT … #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT … #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT … #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT … #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS … /*values for BIOS Page 1 DeviceSettings field */ #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING … #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN … #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN … #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN … #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN … /*defines for BIOS Page 1 UEFIVersion field */ #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK … #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT … #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK … #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT … /*BIOS Page 2 */ pMpi2BootDeviceAdapterOrder_t; pMpi2BootDeviceSasWwid_t; pMpi2BootDeviceEnclosureSlot_t; pMpi2BootDeviceDeviceName_t; pMpi2BiosPage2BootDevice_t; pMpi2BiosPage2_t; #define MPI2_BIOSPAGE2_PAGEVERSION … /*values for BIOS Page 2 BootDeviceForm fields */ #define MPI2_BIOSPAGE2_FORM_MASK … #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED … #define MPI2_BIOSPAGE2_FORM_SAS_WWID … #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT … #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME … /*BIOS Page 3 */ #define MPI2_BIOSPAGE3_NUM_ADAPTER … pMpi2AdapterInfo_t; #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED … #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS … pMpi2AdapterOrderAux_t; pMpi2BiosPage3_t; #define MPI2_BIOSPAGE3_PAGEVERSION … /*values for BIOS Page 3 GlobalFlags */ #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR … #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE … #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE … #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK … #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY … #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY … #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY … /*BIOS Page 4 */ /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumPhys at runtime before using Phy[]. */ pMpi2Bios4Entry_t; pMpi2BiosPage4_t; #define MPI2_BIOSPAGE4_PAGEVERSION … /**************************************************************************** * RAID Volume Config Pages ****************************************************************************/ /*RAID Volume Page 0 */ pMpi2RaidVol0PhysDisk_t; /*defines for the PhysDiskMap field */ #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY … #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY … pMpi2RaidVol0Settings_t; /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ #define MPI2_RAID_HOT_SPARE_POOL_0 … #define MPI2_RAID_HOT_SPARE_POOL_1 … #define MPI2_RAID_HOT_SPARE_POOL_2 … #define MPI2_RAID_HOT_SPARE_POOL_3 … #define MPI2_RAID_HOT_SPARE_POOL_4 … #define MPI2_RAID_HOT_SPARE_POOL_5 … #define MPI2_RAID_HOT_SPARE_POOL_6 … #define MPI2_RAID_HOT_SPARE_POOL_7 … /*RAID Volume Page 0 VolumeSettings defines */ #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX … #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE … #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING … #define MPI2_RAIDVOL0_SETTING_UNCHANGED … #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING … #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING … /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumPhysDisks at runtime before using PhysDisk[]. */ pMpi2RaidVolPage0_t; #define MPI2_RAIDVOLPAGE0_PAGEVERSION … /*values for RAID VolumeState */ #define MPI2_RAID_VOL_STATE_MISSING … #define MPI2_RAID_VOL_STATE_FAILED … #define MPI2_RAID_VOL_STATE_INITIALIZING … #define MPI2_RAID_VOL_STATE_ONLINE … #define MPI2_RAID_VOL_STATE_DEGRADED … #define MPI2_RAID_VOL_STATE_OPTIMAL … /*values for RAID VolumeType */ #define MPI2_RAID_VOL_TYPE_RAID0 … #define MPI2_RAID_VOL_TYPE_RAID1E … #define MPI2_RAID_VOL_TYPE_RAID1 … #define MPI2_RAID_VOL_TYPE_RAID10 … #define MPI2_RAID_VOL_TYPE_UNKNOWN … /*values for RAID Volume Page 0 VolumeStatusFlags field */ #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC … #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING … #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING … #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING … #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT … #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB … #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK … #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION … #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT … #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS … #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT … #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED … #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE … #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR … #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR … #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL … #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE … #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED … #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED … /*values for RAID Volume Page 0 SupportedPhysDisks field */ #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS … #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS … #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL … #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL … /*values for RAID Volume Page 0 InactiveStatus field */ #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE … #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE … #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE … #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE … #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE … #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE … #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED … /*RAID Volume Page 1 */ pMpi2RaidVolPage1_t; #define MPI2_RAIDVOLPAGE1_PAGEVERSION … /**************************************************************************** * RAID Physical Disk Config Pages ****************************************************************************/ /*RAID Physical Disk Page 0 */ pMpi2RaidPhysDisk0Settings_t; /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ pMpi2RaidPhysDisk0InquiryData_t; pMpi2RaidPhysDiskPage0_t; #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION … /*PhysDiskState defines */ #define MPI2_RAID_PD_STATE_NOT_CONFIGURED … #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE … #define MPI2_RAID_PD_STATE_OFFLINE … #define MPI2_RAID_PD_STATE_ONLINE … #define MPI2_RAID_PD_STATE_HOT_SPARE … #define MPI2_RAID_PD_STATE_DEGRADED … #define MPI2_RAID_PD_STATE_REBUILDING … #define MPI2_RAID_PD_STATE_OPTIMAL … /*OfflineReason defines */ #define MPI2_PHYSDISK0_ONLINE … #define MPI2_PHYSDISK0_OFFLINE_MISSING … #define MPI2_PHYSDISK0_OFFLINE_FAILED … #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING … #define MPI2_PHYSDISK0_OFFLINE_REQUESTED … #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED … #define MPI2_PHYSDISK0_OFFLINE_OTHER … /*IncompatibleReason defines */ #define MPI2_PHYSDISK0_COMPATIBLE … #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL … #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE … #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA … #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD … #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA … #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE … #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN … /*PhysDiskAttributes defines */ #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK … #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE … #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE … #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK … #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL … #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL … /*PhysDiskStatusFlags defines */ #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED … #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET … #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED … #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS … #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS … #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME … #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED … #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC … /*RAID Physical Disk Page 1 */ /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumPhysDiskPaths at runtime before using PhysicalDiskPath[]. */ pMpi2RaidPhysDisk1Path_t; /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY … #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN … #define MPI2_RAID_PHYSDISK1_FLAG_INVALID … pMpi2RaidPhysDiskPage1_t; #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION … /**************************************************************************** * values for fields used by several types of SAS Config Pages ****************************************************************************/ /*values for NegotiatedLinkRates fields */ #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL … #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL … #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL … /*link rates used for Negotiated Physical and Logical Link Rate */ #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE … #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED … #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED … #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE … #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR … #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS … #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY … #define MPI2_SAS_NEG_LINK_RATE_1_5 … #define MPI2_SAS_NEG_LINK_RATE_3_0 … #define MPI2_SAS_NEG_LINK_RATE_6_0 … #define MPI25_SAS_NEG_LINK_RATE_12_0 … #define MPI26_SAS_NEG_LINK_RATE_22_5 … /*values for AttachedPhyInfo fields */ #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT … #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS … #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE … #define MPI2_SAS_APHYINFO_REASON_MASK … #define MPI2_SAS_APHYINFO_REASON_UNKNOWN … #define MPI2_SAS_APHYINFO_REASON_POWER_ON … #define MPI2_SAS_APHYINFO_REASON_HARD_RESET … #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL … #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC … #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ … #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER … #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT … #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED … /*values for PhyInfo fields */ #define MPI2_SAS_PHYINFO_PHY_VACANT … #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK … #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION … #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE … #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL … #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER … #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS … #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT … #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS … #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT … #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS … #define MPI2_SAS_PHYINFO_ZONING_ENABLED … #define MPI2_SAS_PHYINFO_REASON_MASK … #define MPI2_SAS_PHYINFO_REASON_UNKNOWN … #define MPI2_SAS_PHYINFO_REASON_POWER_ON … #define MPI2_SAS_PHYINFO_REASON_HARD_RESET … #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL … #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC … #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ … #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER … #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT … #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED … #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED … #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE … #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT … #define MPI2_SAS_PHYINFO_VIRTUAL_PHY … #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME … #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME … #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE … #define MPI2_SAS_PHYINFO_DIRECT_ROUTING … #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING … #define MPI2_SAS_PHYINFO_TABLE_ROUTING … /*values for SAS ProgrammedLinkRate fields */ #define MPI2_SAS_PRATE_MAX_RATE_MASK … #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE … #define MPI2_SAS_PRATE_MAX_RATE_1_5 … #define MPI2_SAS_PRATE_MAX_RATE_3_0 … #define MPI2_SAS_PRATE_MAX_RATE_6_0 … #define MPI25_SAS_PRATE_MAX_RATE_12_0 … #define MPI26_SAS_PRATE_MAX_RATE_22_5 … #define MPI2_SAS_PRATE_MIN_RATE_MASK … #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE … #define MPI2_SAS_PRATE_MIN_RATE_1_5 … #define MPI2_SAS_PRATE_MIN_RATE_3_0 … #define MPI2_SAS_PRATE_MIN_RATE_6_0 … #define MPI25_SAS_PRATE_MIN_RATE_12_0 … #define MPI26_SAS_PRATE_MIN_RATE_22_5 … /*values for SAS HwLinkRate fields */ #define MPI2_SAS_HWRATE_MAX_RATE_MASK … #define MPI2_SAS_HWRATE_MAX_RATE_1_5 … #define MPI2_SAS_HWRATE_MAX_RATE_3_0 … #define MPI2_SAS_HWRATE_MAX_RATE_6_0 … #define MPI25_SAS_HWRATE_MAX_RATE_12_0 … #define MPI26_SAS_HWRATE_MAX_RATE_22_5 … #define MPI2_SAS_HWRATE_MIN_RATE_MASK … #define MPI2_SAS_HWRATE_MIN_RATE_1_5 … #define MPI2_SAS_HWRATE_MIN_RATE_3_0 … #define MPI2_SAS_HWRATE_MIN_RATE_6_0 … #define MPI25_SAS_HWRATE_MIN_RATE_12_0 … #define MPI26_SAS_HWRATE_MIN_RATE_22_5 … /**************************************************************************** * SAS IO Unit Config Pages ****************************************************************************/ /*SAS IO Unit Page 0 */ pMpi2SasIOUnit0PhyData_t; /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumPhys at runtime before using PhyData[]. */ pMpi2SasIOUnitPage0_t; #define MPI2_SASIOUNITPAGE0_PAGEVERSION … /*values for SAS IO Unit Page 0 PortFlags */ #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS … #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG … /*values for SAS IO Unit Page 0 PhyFlags */ #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT … #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT … #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED … #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED … /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ /*see mpi2_sas.h for values for *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ /*values for SAS IO Unit Page 0 DiscoveryStatus */ #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED … #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED … #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED … #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED … #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR … #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE … #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE … #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN … #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK … #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE … #define MPI2_SASIOUNIT0_DS_TABLE_LINK … #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK … #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR … #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED … #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST … #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES … #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT … #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS … #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE … #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED … /*SAS IO Unit Page 1 */ pMpi2SasIOUnit1PhyData_t; /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumPhys at runtime before using PhyData[]. */ pMpi2SasIOUnitPage1_t; #define MPI2_SASIOUNITPAGE1_PAGEVERSION … /*values for SAS IO Unit Page 1 ControlFlags */ #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST … #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX … #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX … #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE … #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT … #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT … #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH … #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT … #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT … #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED … #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED … #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED … #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED … #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL … #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL … #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY … #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION … /*values for SAS IO Unit Page 1 AdditionalControlFlags */ #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT … #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL … #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION … #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION … #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET … #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET … #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET … #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET … #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE … /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK … #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 … /*values for SAS IO Unit Page 1 PortFlags */ #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG … /*values for SAS IO Unit Page 1 PhyFlags */ #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT … #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT … #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE … #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE … /*values for SAS IO Unit Page 1 MaxMinLinkRate */ #define MPI2_SASIOUNIT1_MAX_RATE_MASK … #define MPI2_SASIOUNIT1_MAX_RATE_1_5 … #define MPI2_SASIOUNIT1_MAX_RATE_3_0 … #define MPI2_SASIOUNIT1_MAX_RATE_6_0 … #define MPI25_SASIOUNIT1_MAX_RATE_12_0 … #define MPI26_SASIOUNIT1_MAX_RATE_22_5 … #define MPI2_SASIOUNIT1_MIN_RATE_MASK … #define MPI2_SASIOUNIT1_MIN_RATE_1_5 … #define MPI2_SASIOUNIT1_MIN_RATE_3_0 … #define MPI2_SASIOUNIT1_MIN_RATE_6_0 … #define MPI25_SASIOUNIT1_MIN_RATE_12_0 … #define MPI26_SASIOUNIT1_MIN_RATE_22_5 … /*see mpi2_sas.h for values for *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ /*SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ pMpi2SasIOUnit4SpinupGroup_t; /*defines for SAS IO Unit Page 4 SpinupFlags */ #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG … /* *Host code (drivers, BIOS, utilities, etc.) should leave this define set to *one and check the value returned for NumPhys at runtime. */ #ifndef MPI2_SAS_IOUNIT4_PHY_MAX #define MPI2_SAS_IOUNIT4_PHY_MAX … #endif pMpi2SasIOUnitPage4_t; #define MPI2_SASIOUNITPAGE4_PAGEVERSION … /*defines for Flags field */ #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE … /*defines for PHY field */ #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK … /*SAS IO Unit Page 5 */ pMpi2SasIOUnit5PhyPmSettings_t; /*defines for ControlFlags field */ #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE … #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE … #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE … #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE … /*defines for PortWidthModeGroup field */ #define MPI2_SASIOUNIT5_PWMG_DISABLE … /*defines for InactivityTimerExponent field */ #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER … #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER … #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL … #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL … #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER … #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER … #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL … #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL … #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS … #define MPI2_SASIOUNIT5_ITE_ONE_SECOND … #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS … #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS … #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND … #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS … #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS … #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND … /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumPhys at runtime before using SASPhyPowerManagementSettings[]. */ pMpi2SasIOUnitPage5_t; #define MPI2_SASIOUNITPAGE5_PAGEVERSION … /*SAS IO Unit Page 6 */ pMpi2SasIOUnit6PortWidthModGroupStatus_t; /*defines for CurrentStatus field */ #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE … #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED … #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG … #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN … #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY … #define MPI2_SASIOUNIT6_STATUS_INACTIVE … #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT … #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST … /*defines for CurrentModulation field */ #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT … #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT … #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT … #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT … /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumGroups at runtime before using PortWidthModulationGroupStatus[]. */ pMpi2SasIOUnitPage6_t; #define MPI2_SASIOUNITPAGE6_PAGEVERSION … /*SAS IO Unit Page 7 */ pMpi2SasIOUnit7PortWidthModGroupSettings_t; /*defines for Flags field */ #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION … /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumGroups at runtime before using PortWidthModulationGroupSettings[]. */ pMpi2SasIOUnitPage7_t; #define MPI2_SASIOUNITPAGE7_PAGEVERSION … /*SAS IO Unit Page 8 */ pMpi2SasIOUnitPage8_t; #define MPI2_SASIOUNITPAGE8_PAGEVERSION … /*defines for PowerManagementCapabilities field */ #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD … #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE … #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE … #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE … #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE … #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD … #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE … #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE … #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE … #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE … /*defines for TxRxSleepStatus field */ #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED … #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED … #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE … #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN … /*SAS IO Unit Page 16 */ pMpi2SasIOUnitPage16_t; #define MPI2_SASIOUNITPAGE16_PAGEVERSION … /**************************************************************************** * SAS Expander Config Pages ****************************************************************************/ /*SAS Expander Page 0 */ pMpi2ExpanderPage0_t; #define MPI2_SASEXPANDER0_PAGEVERSION … /*values for SAS Expander Page 0 DiscoveryStatus field */ #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED … #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED … #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED … #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED … #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR … #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE … #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE … #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN … #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK … #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE … #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK … #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK … #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR … #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED … #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST … #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES … #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT … #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS … #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE … #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED … /*values for SAS Expander Page 0 Flags field */ #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY … #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED … #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES … #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES … #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT … #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING … #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT … #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE … #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG … #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS … #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG … /*SAS Expander Page 1 */ pMpi2ExpanderPage1_t; #define MPI2_SASEXPANDER1_PAGEVERSION … /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines *used for the AttachedDeviceInfo field */ /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ /*values for SAS Expander Page 1 DiscoveryInfo field */ #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED … #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE … #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES … /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ /**************************************************************************** * SAS Device Config Pages ****************************************************************************/ /*SAS Device Page 0 */ pMpi2SasDevicePage0_t; #define MPI2_SASDEVICE0_PAGEVERSION … /*values for SAS Device Page 0 AccessStatus field */ #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS … #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED … #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED … #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT … #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION … #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE … #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE … #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED … /*specific values for SATA Init failures */ #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN … #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT … #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG … #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION … #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER … #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN … #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN … #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN … #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION … #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE … #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX … /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ /*values for SAS Device Page 0 Flags field */ #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE … #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH … #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE … #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE … #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE … #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY … #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE … #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE … #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED … #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED … #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED … #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED … #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH … #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE … #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID … #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT … /*SAS Device Page 1 */ pMpi2SasDevicePage1_t; #define MPI2_SASDEVICE1_PAGEVERSION … /**************************************************************************** * SAS PHY Config Pages ****************************************************************************/ /*SAS PHY Page 0 */ pMpi2SasPhyPage0_t; #define MPI2_SASPHY0_PAGEVERSION … /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ /*values for SAS PHY Page 0 Flags field */ #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC … /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ /*SAS PHY Page 1 */ pMpi2SasPhyPage1_t; #define MPI2_SASPHY1_PAGEVERSION … /*SAS PHY Page 2 */ pMpi2SasPhy2PhyEvent_t; /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumPhyEvents at runtime before using PhyEvent[]. */ pMpi2SasPhyPage2_t; #define MPI2_SASPHY2_PAGEVERSION … /*SAS PHY Page 3 */ pMpi2SasPhy3PhyEventConfig_t; /*values for PhyEventCode field */ #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT … #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD … #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR … #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC … #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM … #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW … #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR … #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR … #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT … #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT … #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT … #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT … #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON … #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON … #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK … #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK … #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT … #define MPI2_SASPHY3_EVENT_CODE_CONNECTION … #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED … #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME … #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME … #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME … #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES … #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES … #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES … #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES … #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED … #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED … #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES … #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES … #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW … #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES … #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES … #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES … #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT … #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE … #define MPI2_SASPHY3_EVENT_CODE_RX_AIP … /*Following codes are product specific and in MPI v2.6 and later */ #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME … #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME … #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME … #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT … #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START … #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT … #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN … #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE … #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE … #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE … /*values for the CounterType field */ #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING … #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING … #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE … /*values for the TimeUnits field */ #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS … #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS … #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND … #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS … /*values for the ThresholdFlags field */ #define MPI2_SASPHY3_TFLAGS_PHY_RESET … #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY … /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumPhyEvents at runtime before using PhyEventConfig[]. */ pMpi2SasPhyPage3_t; #define MPI2_SASPHY3_PAGEVERSION … /*SAS PHY Page 4 */ pMpi2SasPhyPage4_t; #define MPI2_SASPHY4_PAGEVERSION … /*values for the Flags field */ #define MPI2_SASPHY4_FLAGS_FRAME_VALID … #define MPI2_SASPHY4_FLAGS_SATA_FRAME … /**************************************************************************** * SAS Port Config Pages ****************************************************************************/ /*SAS Port Page 0 */ pMpi2SasPortPage0_t; #define MPI2_SASPORT0_PAGEVERSION … /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ /**************************************************************************** * SAS Enclosure Config Pages ****************************************************************************/ /*SAS Enclosure Page 0 */ pMpi26EnclosurePage0_t; #define MPI2_SASENCLOSURE0_PAGEVERSION … /*values for SAS Enclosure Page 0 Flags field */ #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_VALID … #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_COLLECTING … #define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID … #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID … #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK … #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN … #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES … #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO … #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO … #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE … #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO … #define MPI26_ENCLOSURE0_PAGEVERSION … /*Values for Enclosure Page 0 Flags field */ #define MPI26_ENCLS0_FLAGS_OEMRD_VALID … #define MPI26_ENCLS0_FLAGS_OEMRD_COLLECTING … #define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID … #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID … #define MPI26_ENCLS0_FLAGS_MNG_MASK … #define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN … #define MPI26_ENCLS0_FLAGS_MNG_IOC_SES … #define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO … #define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO … #define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE … #define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO … /**************************************************************************** * Log Config Page ****************************************************************************/ /*Log Page 0 */ /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumLogEntries at runtime before using LogEntry[]. */ #define MPI2_LOG_0_LOG_DATA_LENGTH … pMpi2Log0Entry_t; /*values for Log Page 0 LogEntry LogEntryQualifier field */ #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED … #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET … #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE … #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC … #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC … pMpi2LogPage0_t; #define MPI2_LOG_0_PAGEVERSION … /**************************************************************************** * RAID Config Page ****************************************************************************/ /*RAID Page 0 */ /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumElements at runtime before using ConfigElement[]. */ pMpi2RaidConfig0ConfigElement_t; /*values for the ElementFlags field */ #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE … #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT … #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT … #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT … #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT … pMpi2RaidConfigurationPage0_t; #define MPI2_RAIDCONFIG0_PAGEVERSION … /*values for RAID Configuration Page 0 Flags field */ #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG … /**************************************************************************** * Driver Persistent Mapping Config Pages ****************************************************************************/ /*Driver Persistent Mapping Page 0 */ pMpi2DriverMap0Entry_t; pMpi2DriverMappingPage0_t; #define MPI2_DRIVERMAPPING0_PAGEVERSION … /*values for Driver Persistent Mapping Page 0 MappingInformation field */ #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK … #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT … #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK … /**************************************************************************** * Ethernet Config Pages ****************************************************************************/ /*Ethernet Page 0 */ /*IP address (union of IPv4 and IPv6) */ pMpi2EthernetIpAddr_t; #define MPI2_ETHERNET_HOST_NAME_LENGTH … pMpi2EthernetPage0_t; #define MPI2_ETHERNETPAGE0_PAGEVERSION … /*values for Ethernet Page 0 Status field */ #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE … #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE … #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED … #define MPI2_ETHPG0_STATUS_DEFAULT_IF … #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED … #define MPI2_ETHPG0_STATUS_TELNET_ENABLED … #define MPI2_ETHPG0_STATUS_SSH2_ENABLED … #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED … #define MPI2_ETHPG0_STATUS_IPV6_ENABLED … #define MPI2_ETHPG0_STATUS_IPV4_ENABLED … #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES … #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED … /*values for Ethernet Page 0 MediaState field */ #define MPI2_ETHPG0_MS_DUPLEX_MASK … #define MPI2_ETHPG0_MS_HALF_DUPLEX … #define MPI2_ETHPG0_MS_FULL_DUPLEX … #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK … #define MPI2_ETHPG0_MS_NOT_CONNECTED … #define MPI2_ETHPG0_MS_10MBIT … #define MPI2_ETHPG0_MS_100MBIT … #define MPI2_ETHPG0_MS_1GBIT … /*Ethernet Page 1 */ pMpi2EthernetPage1_t; #define MPI2_ETHERNETPAGE1_PAGEVERSION … /*values for Ethernet Page 1 Flags field */ #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF … #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD … #define MPI2_ETHPG1_FLAG_ENABLE_TELNET … #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 … #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT … #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 … #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 … #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES … #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF … /*values for Ethernet Page 1 MediaState field */ #define MPI2_ETHPG1_MS_DUPLEX_MASK … #define MPI2_ETHPG1_MS_HALF_DUPLEX … #define MPI2_ETHPG1_MS_FULL_DUPLEX … #define MPI2_ETHPG1_MS_DATA_RATE_MASK … #define MPI2_ETHPG1_MS_DATA_RATE_AUTO … #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT … #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT … #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT … /**************************************************************************** * Extended Manufacturing Config Pages ****************************************************************************/ /* *Generic structure to use for product-specific extended manufacturing pages *(currently Extended Manufacturing Page 40 through Extended Manufacturing *Page 60). */ pMpi2ExtManufacturingPagePS_t; /*PageVersion should be provided by product-specific code */ /**************************************************************************** * values for fields used by several types of PCIe Config Pages ****************************************************************************/ /*values for NegotiatedLinkRates fields */ #define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL … /*link rates used for Negotiated Physical Link Rate */ #define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN … #define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED … #define MPI26_PCIE_NEG_LINK_RATE_2_5 … #define MPI26_PCIE_NEG_LINK_RATE_5_0 … #define MPI26_PCIE_NEG_LINK_RATE_8_0 … #define MPI26_PCIE_NEG_LINK_RATE_16_0 … /**************************************************************************** * PCIe IO Unit Config Pages (MPI v2.6 and later) ****************************************************************************/ /*PCIe IO Unit Page 0 */ pMpi26PCIeIOUnit0PhyData_t; /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumPhys at runtime before using PhyData[]. */ pMpi26PCIeIOUnitPage0_t; #define MPI26_PCIEIOUNITPAGE0_PAGEVERSION … /*values for PCIe IO Unit Page 0 LinkFlags */ #define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS … /*values for PCIe IO Unit Page 0 PhyFlags */ #define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED … /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo *values */ /*values for PCIe IO Unit Page 0 EnumerationStatus */ #define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED … #define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED … /*PCIe IO Unit Page 1 */ pMpi26PCIeIOUnit1PhyData_t; /*values for LinkFlags */ #define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK … #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN … #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN … /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumPhys at runtime before using PhyData[]. */ pMpi26PCIeIOUnitPage1_t; #define MPI26_PCIEIOUNITPAGE1_PAGEVERSION … /*values for PCIe IO Unit Page 1 PhyFlags */ #define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE … #define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY … /*values for PCIe IO Unit Page 1 MaxMinLinkRate */ #define MPI26_PCIEIOUNIT1_MAX_RATE_MASK … #define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT … #define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 … #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 … #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 … #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 … /*values for PCIe IO Unit Page 1 DMDReportPCIe */ #define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_MASK … #define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_1_SEC … #define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_16_SEC … #define MPI26_PCIEIOUNIT1_DMDRPT_DELAY_TIME_MASK … /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo *values */ /**************************************************************************** * PCIe Switch Config Pages (MPI v2.6 and later) ****************************************************************************/ /*PCIe Switch Page 0 */ pMpi26PCIeSwitchPage0_t; #define MPI26_PCIESWITCH0_PAGEVERSION … /*PCIe Switch Page 1 */ pMpi26PCIeSwitchPage1_t; #define MPI26_PCIESWITCH1_PAGEVERSION … /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ /* defines for the Flags field */ #define MPI26_PCIESWITCH1_2_RETIMER_PRESENCE … #define MPI26_PCIESWITCH1_RETIMER_PRESENCE … /**************************************************************************** * PCIe Device Config Pages (MPI v2.6 and later) ****************************************************************************/ /*PCIe Device Page 0 */ pMpi26PCIeDevicePage0_t; #define MPI26_PCIEDEVICE0_PAGEVERSION … /*values for PCIe Device Page 0 AccessStatus field */ #define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS … #define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION … #define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED … #define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED … #define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED … #define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE … #define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED … #define MPI26_PCIEDEV0_ASTATUS_UNKNOWN … #define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT … #define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED … #define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED … #define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED … #define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED … #define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED … #define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED … #define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT … #define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS … #define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX … /*see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo *field */ /*values for PCIe Device Page 0 Flags field*/ #define MPI26_PCIEDEV0_FLAGS_2_RETIMER_PRESENCE … #define MPI26_PCIEDEV0_FLAGS_RETIMER_PRESENCE … #define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE … #define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH … #define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE … #define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION … #define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION … #define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE … #define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED … #define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED … #define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED … #define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED … #define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID … #define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT … /* values for PCIe Device Page 0 SupportedLinkRates field */ #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED … #define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED … #define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED … #define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED … /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ /*PCIe Device Page 2 */ pMpi26PCIeDevicePage2_t; #define MPI26_PCIEDEVICE2_PAGEVERSION … /*defines for PCIe Device Page 2 Capabilities field */ #define MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN … #define MPI26_PCIEDEV2_CAP_SGL_FORMAT … #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT … #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT … /* Defines for the NOIOB field */ #define MPI26_PCIEDEV2_NOIOB_UNSUPPORTED … /**************************************************************************** * PCIe Link Config Pages (MPI v2.6 and later) ****************************************************************************/ /*PCIe Link Page 1 */ pMpi26PcieLinkPage1_t; #define MPI26_PCIELINK1_PAGEVERSION … /*PCIe Link Page 2 */ pMpi26PcieLink2LinkEvent_t; /*use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */ /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumLinkEvents at runtime before using LinkEvent[]. */ pMpi26PcieLinkPage2_t; #define MPI26_PCIELINK2_PAGEVERSION … /*PCIe Link Page 3 */ pMpi26PcieLink3LinkEventConfig_t; /*values for LinkEventCode field */ #define MPI26_PCIELINK3_EVTCODE_NO_EVENT … #define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED … #define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED … #define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED … #define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED … #define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED … #define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED … #define MPI26_PCIELINK3_EVTCODE_POISONED_TLP … #define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP … #define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP … #define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE … #define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE … #define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE … #define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE … #define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE … #define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE … #define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR … #define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR … #define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR … /*values for the CounterType field */ #define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING … #define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING … #define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE … /*values for the TimeUnits field */ #define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS … #define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS … #define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND … #define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS … /*values for the ThresholdFlags field */ #define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY … /* *Host code (drivers, BIOS, utilities, etc.) should check the value returned *for NumLinkEvents at runtime before using LinkEventConfig[]. */ pMpi26PcieLinkPage3_t; #define MPI26_PCIELINK3_PAGEVERSION … #endif
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