/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2017-2023 Broadcom Inc. All rights reserved. */ #ifndef MPI30_CNFG_H #define MPI30_CNFG_H … #define MPI3_CONFIG_PAGETYPE_IO_UNIT … #define MPI3_CONFIG_PAGETYPE_MANUFACTURING … #define MPI3_CONFIG_PAGETYPE_IOC … #define MPI3_CONFIG_PAGETYPE_DRIVER … #define MPI3_CONFIG_PAGETYPE_SECURITY … #define MPI3_CONFIG_PAGETYPE_ENCLOSURE … #define MPI3_CONFIG_PAGETYPE_DEVICE … #define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT … #define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER … #define MPI3_CONFIG_PAGETYPE_SAS_PHY … #define MPI3_CONFIG_PAGETYPE_SAS_PORT … #define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT … #define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH … #define MPI3_CONFIG_PAGETYPE_PCIE_LINK … #define MPI3_CONFIG_PAGEATTR_MASK … #define MPI3_CONFIG_PAGEATTR_READ_ONLY … #define MPI3_CONFIG_PAGEATTR_CHANGEABLE … #define MPI3_CONFIG_PAGEATTR_PERSISTENT … #define MPI3_CONFIG_ACTION_PAGE_HEADER … #define MPI3_CONFIG_ACTION_READ_DEFAULT … #define MPI3_CONFIG_ACTION_READ_CURRENT … #define MPI3_CONFIG_ACTION_WRITE_CURRENT … #define MPI3_CONFIG_ACTION_READ_PERSISTENT … #define MPI3_CONFIG_ACTION_WRITE_PERSISTENT … #define MPI3_DEVICE_PGAD_FORM_MASK … #define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE … #define MPI3_DEVICE_PGAD_FORM_HANDLE … #define MPI3_DEVICE_PGAD_HANDLE_MASK … #define MPI3_SAS_EXPAND_PGAD_FORM_MASK … #define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE … #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM … #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE … #define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK … #define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT … #define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK … #define MPI3_SAS_PHY_PGAD_FORM_MASK … #define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER … #define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK … #define MPI3_SASPORT_PGAD_FORM_MASK … #define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT … #define MPI3_SASPORT_PGAD_FORM_PORT_NUM … #define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK … #define MPI3_ENCLOS_PGAD_FORM_MASK … #define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE … #define MPI3_ENCLOS_PGAD_FORM_HANDLE … #define MPI3_ENCLOS_PGAD_HANDLE_MASK … #define MPI3_PCIE_SWITCH_PGAD_FORM_MASK … #define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE … #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM … #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE … #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK … #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT … #define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK … #define MPI3_PCIE_LINK_PGAD_FORM_MASK … #define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK … #define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM … #define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK … #define MPI3_SECURITY_PGAD_FORM_MASK … #define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT … #define MPI3_SECURITY_PGAD_FORM_SLOT_NUM … #define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK … #define MPI3_SECURITY_PGAD_SLOT_GROUP_SHIFT … #define MPI3_SECURITY_PGAD_SLOT_MASK … struct mpi3_config_request { … }; struct mpi3_config_page_header { … }; #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK … #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT … #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK … #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT … #define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE … #define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED … #define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED … #define MPI3_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE … #define MPI3_SAS_NEG_LINK_RATE_PORT_SELECTOR … #define MPI3_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS … #define MPI3_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY … #define MPI3_SAS_NEG_LINK_RATE_1_5 … #define MPI3_SAS_NEG_LINK_RATE_3_0 … #define MPI3_SAS_NEG_LINK_RATE_6_0 … #define MPI3_SAS_NEG_LINK_RATE_12_0 … #define MPI3_SAS_NEG_LINK_RATE_22_5 … #define MPI3_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT … #define MPI3_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS … #define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE … #define MPI3_SAS_APHYINFO_REASON_MASK … #define MPI3_SAS_APHYINFO_REASON_UNKNOWN … #define MPI3_SAS_APHYINFO_REASON_POWER_ON … #define MPI3_SAS_APHYINFO_REASON_HARD_RESET … #define MPI3_SAS_APHYINFO_REASON_SMP_PHY_CONTROL … #define MPI3_SAS_APHYINFO_REASON_LOSS_OF_SYNC … #define MPI3_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ … #define MPI3_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER … #define MPI3_SAS_APHYINFO_REASON_BREAK_TIMEOUT … #define MPI3_SAS_APHYINFO_REASON_PHY_TEST_STOPPED … #define MPI3_SAS_APHYINFO_REASON_EXP_REDUCED_FUNC … #define MPI3_SAS_PHYINFO_STATUS_MASK … #define MPI3_SAS_PHYINFO_STATUS_SHIFT … #define MPI3_SAS_PHYINFO_STATUS_ACCESSIBLE … #define MPI3_SAS_PHYINFO_STATUS_NOT_EXIST … #define MPI3_SAS_PHYINFO_STATUS_VACANT … #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK … #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE … #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL … #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER … #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_MASK … #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_SHIFT … #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_MASK … #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_SHIFT … #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_MASK … #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_SHIFT … #define MPI3_SAS_PHYINFO_ZONE_GROUP_PERSISTENT … #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_WITHIN … #define MPI3_SAS_PHYINFO_ZONING_ENABLED … #define MPI3_SAS_PHYINFO_REASON_MASK … #define MPI3_SAS_PHYINFO_REASON_UNKNOWN … #define MPI3_SAS_PHYINFO_REASON_POWER_ON … #define MPI3_SAS_PHYINFO_REASON_HARD_RESET … #define MPI3_SAS_PHYINFO_REASON_SMP_PHY_CONTROL … #define MPI3_SAS_PHYINFO_REASON_LOSS_OF_SYNC … #define MPI3_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ … #define MPI3_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER … #define MPI3_SAS_PHYINFO_REASON_BREAK_TIMEOUT … #define MPI3_SAS_PHYINFO_REASON_PHY_TEST_STOPPED … #define MPI3_SAS_PHYINFO_REASON_EXP_REDUCED_FUNC … #define MPI3_SAS_PHYINFO_SATA_PORT_ACTIVE … #define MPI3_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT … #define MPI3_SAS_PHYINFO_VIRTUAL_PHY … #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_MASK … #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT … #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK … #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT … #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE … #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE … #define MPI3_SAS_PRATE_MAX_RATE_MASK … #define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE … #define MPI3_SAS_PRATE_MAX_RATE_1_5 … #define MPI3_SAS_PRATE_MAX_RATE_3_0 … #define MPI3_SAS_PRATE_MAX_RATE_6_0 … #define MPI3_SAS_PRATE_MAX_RATE_12_0 … #define MPI3_SAS_PRATE_MAX_RATE_22_5 … #define MPI3_SAS_PRATE_MIN_RATE_MASK … #define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE … #define MPI3_SAS_PRATE_MIN_RATE_1_5 … #define MPI3_SAS_PRATE_MIN_RATE_3_0 … #define MPI3_SAS_PRATE_MIN_RATE_6_0 … #define MPI3_SAS_PRATE_MIN_RATE_12_0 … #define MPI3_SAS_PRATE_MIN_RATE_22_5 … #define MPI3_SAS_HWRATE_MAX_RATE_MASK … #define MPI3_SAS_HWRATE_MAX_RATE_1_5 … #define MPI3_SAS_HWRATE_MAX_RATE_3_0 … #define MPI3_SAS_HWRATE_MAX_RATE_6_0 … #define MPI3_SAS_HWRATE_MAX_RATE_12_0 … #define MPI3_SAS_HWRATE_MAX_RATE_22_5 … #define MPI3_SAS_HWRATE_MIN_RATE_MASK … #define MPI3_SAS_HWRATE_MIN_RATE_1_5 … #define MPI3_SAS_HWRATE_MIN_RATE_3_0 … #define MPI3_SAS_HWRATE_MIN_RATE_6_0 … #define MPI3_SAS_HWRATE_MIN_RATE_12_0 … #define MPI3_SAS_HWRATE_MIN_RATE_22_5 … #define MPI3_SLOT_INVALID … #define MPI3_SLOT_INDEX_INVALID … #define MPI3_LINK_CHANGE_COUNT_INVALID … #define MPI3_RATE_CHANGE_COUNT_INVALID … #define MPI3_TEMP_SENSOR_LOCATION_INTERNAL … #define MPI3_TEMP_SENSOR_LOCATION_INLET … #define MPI3_TEMP_SENSOR_LOCATION_OUTLET … #define MPI3_TEMP_SENSOR_LOCATION_DRAM … #define MPI3_MFGPAGE_VENDORID_BROADCOM … #define MPI3_MFGPAGE_DEVID_SAS4116 … #define MPI3_MFGPAGE_DEVID_SAS5116_MPI … #define MPI3_MFGPAGE_DEVID_SAS5116_NVME … #define MPI3_MFGPAGE_DEVID_SAS5116_MPI_MGMT … #define MPI3_MFGPAGE_DEVID_SAS5116_NVME_MGMT … #define MPI3_MFGPAGE_DEVID_SAS5116_PCIE_SWITCH … struct mpi3_man_page0 { … }; #define MPI3_MAN0_PAGEVERSION … #define MPI3_MAN0_FLAGS_SWITCH_PRESENT … #define MPI3_MAN0_FLAGS_EXPANDER_PRESENT … #define MPI3_MAN1_VPD_SIZE … struct mpi3_man_page1 { … }; #define MPI3_MAN1_PAGEVERSION … struct mpi3_man_page2 { … }; #define MPI3_MAN2_PAGEVERSION … #define MPI3_MAN2_FLAGS_TRACER_PRESENT … struct mpi3_man5_phy_entry { … }; #ifndef MPI3_MAN5_PHY_MAX #define MPI3_MAN5_PHY_MAX … #endif struct mpi3_man_page5 { … }; #define MPI3_MAN5_PAGEVERSION … struct mpi3_man6_gpio_entry { … }; #define MPI3_MAN6_GPIO_FUNCTION_GENERIC … #define MPI3_MAN6_GPIO_FUNCTION_ALTERNATE … #define MPI3_MAN6_GPIO_FUNCTION_EXT_INTERRUPT … #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_ACTIVITY … #define MPI3_MAN6_GPIO_FUNCTION_OVER_TEMPERATURE … #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_GREEN … #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW … #define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT … #define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE … #define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET … #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET … #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT … #define MPI3_MAN6_GPIO_FUNCTION_PBLP_STATUS_CHANGE … #define MPI3_MAN6_GPIO_FUNCTION_EPACK_ONLINE … #define MPI3_MAN6_GPIO_FUNCTION_EPACK_FAULT … #define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE … #define MPI3_MAN6_GPIO_FUNCTION_LICENSE … #define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL … #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET_CLAMP … #define MPI3_MAN6_GPIO_FUNCTION_AUXILIARY_POWER … #define MPI3_MAN6_GPIO_FUNCTION_RAID_DATA_CACHE_DIRTY … #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_CONTROL … #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_FAULT … #define MPI3_MAN6_GPIO_FUNCTION_POWER_BRAKE … #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK … #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI … #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID … #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK … #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC … #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT … #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT … #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_ACK_REQUIRED … #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK … #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE … #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL … #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP … #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP … #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT … #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE … #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE … #define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON … #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK … #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE … #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE … #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK … #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM … #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM … #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM … #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_33OHM … #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_MASK … #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_SHIFT … #define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH … #define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED … #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK … #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT … #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT … #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT … #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_PUSH_PULL_OUTPUT … #ifndef MPI3_MAN6_GPIO_MAX #define MPI3_MAN6_GPIO_MAX … #endif struct mpi3_man_page6 { … }; #define MPI3_MAN6_PAGEVERSION … #define MPI3_MAN6_FLAGS_HEARTBEAT_LED_DISABLED … struct mpi3_man7_receptacle_info { … }; #define MPI3_MAN7_LOCATION_UNKNOWN … #define MPI3_MAN7_LOCATION_INTERNAL … #define MPI3_MAN7_LOCATION_EXTERNAL … #define MPI3_MAN7_LOCATION_VIRTUAL … #define MPI3_MAN7_LOCATION_HOST … #define MPI3_MAN7_CONNECTOR_TYPE_NO_INFO … #define MPI3_MAN7_PEDCLK_ROUTING_MASK … #define MPI3_MAN7_PEDCLK_ROUTING_DIRECT … #define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER … #define MPI3_MAN7_PEDCLK_ID_MASK … #ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX #define MPI3_MAN7_RECEPTACLE_INFO_MAX … #endif struct mpi3_man_page7 { … }; #define MPI3_MAN7_PAGEVERSION … #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK … #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0 … #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1 … struct mpi3_man8_phy_info { … }; #define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_NOT_ASSOCIATED … #define MPI3_MAN8_PHY_INFO_CONNECTOR_LANE_NOT_ASSOCIATED … #ifndef MPI3_MAN8_PHY_INFO_MAX #define MPI3_MAN8_PHY_INFO_MAX … #endif struct mpi3_man_page8 { … }; #define MPI3_MAN8_PAGEVERSION … struct mpi3_man9_rsrc_entry { … }; enum mpi3_man9_resources { … }; #define MPI3_MAN9_MIN_OUTSTANDING_REQS … #define MPI3_MAN9_MAX_OUTSTANDING_REQS … #define MPI3_MAN9_MIN_TARGET_CMDS … #define MPI3_MAN9_MAX_TARGET_CMDS … #define MPI3_MAN9_MIN_NVME_TARGETS … #define MPI3_MAN9_MIN_INITIATORS … #define MPI3_MAN9_MIN_VDS … #define MPI3_MAN9_MIN_ENCLOSURES … #define MPI3_MAN9_MAX_ENCLOSURES … #define MPI3_MAN9_MIN_ENCLOSURE_PHYS … #define MPI3_MAN9_MIN_EXPANDERS … #define MPI3_MAN9_MAX_EXPANDERS … #define MPI3_MAN9_MIN_PCIE_SWITCHES … #define MPI3_MAN9_MIN_HOST_PD_DRIVES … #define MPI3_MAN9_ADV_HOST_PD_DRIVES … #define MPI3_MAN9_RAID_PD_DRIVES … #define MPI3_MAN9_DRIVER_DIAG_BUFFER … #define MPI3_MAN9_MIN_NAMESPACE_COUNT … #define MPI3_MAN9_MIN_EXPANDERS … #define MPI3_MAN9_MAX_EXPANDERS … struct mpi3_man_page9 { … }; #define MPI3_MAN9_PAGEVERSION … struct mpi3_man10_istwi_ctrlr_entry { … }; #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK … #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100K … #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400K … #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_TARGET_ENABLED … #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_INITIATOR_ENABLED … #ifndef MPI3_MAN10_ISTWI_CTRLR_MAX #define MPI3_MAN10_ISTWI_CTRLR_MAX … #endif struct mpi3_man_page10 { … }; #define MPI3_MAN10_PAGEVERSION … struct mpi3_man11_mux_device_format { … }; struct mpi3_man11_temp_sensor_device_format { … }; #define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654 … #define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442 … #define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476 … #define MPI3_MAN11_TEMP_SENSOR_TYPE_SE97B … #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_MASK … #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_SHIFT … #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED … struct mpi3_man11_seeprom_device_format { … }; #define MPI3_MAN11_SEEPROM_SIZE_1KBITS … #define MPI3_MAN11_SEEPROM_SIZE_2KBITS … #define MPI3_MAN11_SEEPROM_SIZE_4KBITS … #define MPI3_MAN11_SEEPROM_SIZE_8KBITS … #define MPI3_MAN11_SEEPROM_SIZE_16KBITS … #define MPI3_MAN11_SEEPROM_SIZE_32KBITS … #define MPI3_MAN11_SEEPROM_SIZE_64KBITS … #define MPI3_MAN11_SEEPROM_SIZE_128KBITS … struct mpi3_man11_ddr_spd_device_format { … }; struct mpi3_man11_cable_mgmt_device_format { … }; #define MPI3_MAN11_CABLE_MGMT_TYPE_SFF_8636 … struct mpi3_man11_bkplane_spec_ubm_format { … }; #define MPI3_MAN11_BKPLANE_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED … #define MPI3_MAN11_BKPLANE_UBM_FLAGS_FORCE_POLLING … #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_MASK … #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_SHIFT … #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_MASK … #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_SHIFT … struct mpi3_man11_bkplane_spec_non_ubm_format { … }; #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_MASK … #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_SHIFT … #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED … #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_MASK … #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_4 … #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_2 … #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_1 … #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_MASK … #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_GPIO … #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_REG … #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_MASK … #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_SHIFT … #define MPI3_MAN11_BKPLANE_NON_UBM_TYPE_VPP … mpi3_man11_bkplane_spec_format; struct mpi3_man11_bkplane_mgmt_device_format { … }; #define MPI3_MAN11_BKPLANE_MGMT_TYPE_UBM … #define MPI3_MAN11_BKPLANE_MGMT_TYPE_NON_UBM … #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_MASK … #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_SHIFT … #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_MASK … #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_SHIFT … struct mpi3_man11_gas_gauge_device_format { … }; #define MPI3_MAN11_GAS_GAUGE_TYPE_STANDARD … struct mpi3_man11_mgmt_ctrlr_device_format { … }; struct mpi3_man11_board_fan_device_format { … }; #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_MASK … #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_AMC6821 … mpi3_man11_device_specific_format; struct mpi3_man11_istwi_device_format { … }; #define MPI3_MAN11_ISTWI_DEVTYPE_MUX … #define MPI3_MAN11_ISTWI_DEVTYPE_TEMP_SENSOR … #define MPI3_MAN11_ISTWI_DEVTYPE_SEEPROM … #define MPI3_MAN11_ISTWI_DEVTYPE_DDR_SPD … #define MPI3_MAN11_ISTWI_DEVTYPE_CABLE_MGMT … #define MPI3_MAN11_ISTWI_DEVTYPE_BACKPLANE_MGMT … #define MPI3_MAN11_ISTWI_DEVTYPE_GAS_GAUGE … #define MPI3_MAN11_ISTWI_DEVTYPE_MGMT_CONTROLLER … #define MPI3_MAN11_ISTWI_DEVTYPE_BOARD_FAN … #define MPI3_MAN11_ISTWI_FLAGS_MUX_PRESENT … #ifndef MPI3_MAN11_ISTWI_DEVICE_MAX #define MPI3_MAN11_ISTWI_DEVICE_MAX … #endif struct mpi3_man_page11 { … }; #define MPI3_MAN11_PAGEVERSION … #ifndef MPI3_MAN12_NUM_SGPIO_MAX #define MPI3_MAN12_NUM_SGPIO_MAX … #endif struct mpi3_man12_sgpio_info { … }; struct mpi3_man_page12 { … }; #define MPI3_MAN12_PAGEVERSION … #define MPI3_MAN12_FLAGS_ERROR_PRESENCE_ENABLED … #define MPI3_MAN12_FLAGS_ACTIVITY_INVERT_ENABLED … #define MPI3_MAN12_FLAGS_GROUP_ID_DISABLED … #define MPI3_MAN12_FLAGS_SIO_CLK_FILTER_ENABLED … #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_MASK … #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_PUSH_PULL … #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_OPEN_DRAIN … #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_MASK … #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_PUSH_PULL … #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_OPEN_DRAIN … #define MPI3_MAN12_SIO_CLK_FREQ_MIN … #define MPI3_MAN12_SIO_CLK_FREQ_MAX … #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_MASK … #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_SHIFT … #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_MASK … #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_SHIFT … #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_MASK … #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_SHIFT … #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_MASK … #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_SHIFT … #define MPI3_MAN12_PATTERN_RATE_MASK … #define MPI3_MAN12_PATTERN_RATE_2_HZ … #define MPI3_MAN12_PATTERN_RATE_4_HZ … #define MPI3_MAN12_PATTERN_RATE_8_HZ … #define MPI3_MAN12_PATTERN_RATE_16_HZ … #define MPI3_MAN12_PATTERN_RATE_10_HZ … #define MPI3_MAN12_PATTERN_RATE_20_HZ … #define MPI3_MAN12_PATTERN_RATE_40_HZ … #define MPI3_MAN12_PATTERN_LENGTH_MASK … #define MPI3_MAN12_PATTERN_LENGTH_SHIFT … #define MPI3_MAN12_PATTERN_BIT_PATTERN_MASK … #define MPI3_MAN12_PATTERN_BIT_PATTERN_SHIFT … #ifndef MPI3_MAN13_NUM_TRANSLATION_MAX #define MPI3_MAN13_NUM_TRANSLATION_MAX … #endif struct mpi3_man13_translation_info { … }; #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_FAULT … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_OFF … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_ACTIVITY … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DO_NOT_REMOVE … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_MISSING … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_INSERT … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REMOVAL … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IDENTIFY … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_OK … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_RESERVED_DEVICE … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_HOT_SPARE … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_CONSISTENCY_CHECK … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_CRITICAL_ARRAY … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_FAILED_ARRAY … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP_ABORT … #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_PREDICTED_FAILURE … #define MPI3_MAN13_BLINK_PATTERN_FORCE_OFF … #define MPI3_MAN13_BLINK_PATTERN_FORCE_ON … #define MPI3_MAN13_BLINK_PATTERN_PATTERN_0 … #define MPI3_MAN13_BLINK_PATTERN_PATTERN_1 … #define MPI3_MAN13_BLINK_PATTERN_PATTERN_2 … #define MPI3_MAN13_BLINK_PATTERN_PATTERN_3 … #define MPI3_MAN13_BLINK_PATTERN_PATTERN_4 … #define MPI3_MAN13_BLINK_PATTERN_PATTERN_5 … #define MPI3_MAN13_BLINK_PATTERN_PATTERN_6 … #define MPI3_MAN13_BLINK_PATTERN_PATTERN_7 … #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY … #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY_TRAIL … struct mpi3_man_page13 { … }; #define MPI3_MAN13_PAGEVERSION … struct mpi3_man_page14 { … }; #define MPI3_MAN14_PAGEVERSION … #define MPI3_MAN14_NUMSLOTS_MAX … #ifndef MPI3_MAN15_VERSION_RECORD_MAX #define MPI3_MAN15_VERSION_RECORD_MAX … #endif struct mpi3_man15_version_record { … }; struct mpi3_man_page15 { … }; #define MPI3_MAN15_PAGEVERSION … #ifndef MPI3_MAN16_CERT_ALGO_MAX #define MPI3_MAN16_CERT_ALGO_MAX … #endif struct mpi3_man16_certificate_algorithm { … }; struct mpi3_man_page16 { … }; #define MPI3_MAN16_PAGEVERSION … #ifndef MPI3_MAN17_HASH_ALGORITHM_MAX #define MPI3_MAN17_HASH_ALGORITHM_MAX … #endif struct mpi3_man17_hash_algorithm { … }; struct mpi3_man_page17 { … }; #define MPI3_MAN17_PAGEVERSION … struct mpi3_man_page20 { … }; #define MPI3_MAN20_PAGEVERSION … #define MPI3_MAN20_ALLOWEDPERSON_RAID_MASK … #define MPI3_MAN20_ALLOWEDPERSON_RAID_ALLOWED … #define MPI3_MAN20_ALLOWEDPERSON_RAID_NOT_ALLOWED … #define MPI3_MAN20_ALLOWEDPERSON_EHBA_MASK … #define MPI3_MAN20_ALLOWEDPERSON_EHBA_ALLOWED … #define MPI3_MAN20_ALLOWEDPERSON_EHBA_NOT_ALLOWED … #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_MASK … #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_ENABLED … #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_DISABLED … struct mpi3_man_page21 { … }; #define MPI3_MAN21_PAGEVERSION … #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK … #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK … #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW … #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN … #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK … #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW … #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT … #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK … #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT … #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC … #ifndef MPI3_MAN_PROD_SPECIFIC_MAX #define MPI3_MAN_PROD_SPECIFIC_MAX … #endif struct mpi3_man_page_product_specific { … }; struct mpi3_io_unit_page0 { … }; #define MPI3_IOUNIT0_PAGEVERSION … struct mpi3_io_unit_page1 { … }; #define MPI3_IOUNIT1_PAGEVERSION … #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_MASK … #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_ENABLE … #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_DISABLE … #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_NO_MODIFY … #define MPI3_IOUNIT1_FLAGS_ATA_SECURITY_FREEZE_LOCK … #define MPI3_IOUNIT1_FLAGS_WRITE_SAME_BUFFER … #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_MASK … #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_ENABLE … #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_DISABLE … #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_UNCHANGED … #define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_MASK … #define MPI3_IOUNIT1_DMD_REPORT_UNIT_16_SEC … #ifndef MPI3_IO_UNIT2_GPIO_VAL_MAX #define MPI3_IO_UNIT2_GPIO_VAL_MAX … #endif struct mpi3_io_unit_page2 { … }; #define MPI3_IOUNIT2_PAGEVERSION … #define MPI3_IOUNIT2_GPIO_FUNCTION_MASK … #define MPI3_IOUNIT2_GPIO_FUNCTION_SHIFT … #define MPI3_IOUNIT2_GPIO_SETTING_MASK … #define MPI3_IOUNIT2_GPIO_SETTING_OFF … #define MPI3_IOUNIT2_GPIO_SETTING_ON … struct mpi3_io_unit3_sensor { … }; #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_EVENT_ENABLED … #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_ACTION_ENABLED … #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_EVENT_ENABLED … #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_ACTION_ENABLED … #define MPI3_IOUNIT3_SENSOR_FLAGS_WARNING_EVENT_ENABLED … #ifndef MPI3_IO_UNIT3_SENSOR_MAX #define MPI3_IO_UNIT3_SENSOR_MAX … #endif struct mpi3_io_unit_page3 { … }; #define MPI3_IOUNIT3_PAGEVERSION … struct mpi3_io_unit4_sensor { … }; #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_MASK … #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_SHIFT … #define MPI3_IOUNIT4_SENSOR_FLAGS_TEMP_VALID … #define MPI3_IOUNIT4_SENSOR_ISTWI_INDEX_INTERNAL … #define MPI3_IOUNIT4_SENSOR_CHANNEL_RESERVED … #ifndef MPI3_IO_UNIT4_SENSOR_MAX #define MPI3_IO_UNIT4_SENSOR_MAX … #endif struct mpi3_io_unit_page4 { … }; #define MPI3_IOUNIT4_PAGEVERSION … struct mpi3_io_unit5_spinup_group { … }; #define MPI3_IOUNIT5_SPINUP_FLAGS_DISABLE … #ifndef MPI3_IO_UNIT5_PHY_MAX #define MPI3_IO_UNIT5_PHY_MAX … #endif struct mpi3_io_unit_page5 { … }; #define MPI3_IOUNIT5_PAGEVERSION … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NO_ACTION … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_ATTACHED … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_EXPANDER_ATTACHED … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SWITCH_ATTACHED … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_EXPANDER … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_SWITCH … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_MASK … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_SHIFT … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_MASK … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_SHIFT … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_MASK … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_SHIFT … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_MASK … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_SHIFT … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_MASK … #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_SHIFT … #define MPI3_IOUNIT5_FLAGS_SATAPUIS_MASK … #define MPI3_IOUNIT5_FLAGS_SATAPUIS_NOT_SUPPORTED … #define MPI3_IOUNIT5_FLAGS_SATAPUIS_OS_CONTROLLED … #define MPI3_IOUNIT5_FLAGS_SATAPUIS_APP_CONTROLLED … #define MPI3_IOUNIT5_FLAGS_SATAPUIS_BLOCKED … #define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP … #define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE … #define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK … struct mpi3_io_unit_page6 { … }; #define MPI3_IOUNIT6_PAGEVERSION … #define MPI3_IOUNIT6_FLAGS_ACT_CABLE_PWR_EXC … #ifndef MPI3_IOUNIT8_DIGEST_MAX #define MPI3_IOUNIT8_DIGEST_MAX … #endif mpi3_iounit8_digest; struct mpi3_io_unit_page8 { … }; #define MPI3_IOUNIT8_PAGEVERSION … #define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG … #define MPI3_IOUNIT8_SBMODE_HARD_SECURE … #define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE … #define MPI3_IOUNIT8_SBSTATE_SVN_UPDATE_PENDING … #define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING … #define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED … struct mpi3_io_unit_page9 { … }; #define MPI3_IOUNIT9_PAGEVERSION … #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_MASK … #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_SHIFT … #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_NONE … #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_RECEPTACLE … #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_BACKPLANE_TYPE … #define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED … #define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN … struct mpi3_io_unit_page10 { … }; #define MPI3_IOUNIT10_PAGEVERSION … #define MPI3_IOUNIT10_FLAGS_VALID … #define MPI3_IOUNIT10_FLAGS_ACTIVEID_MASK … #define MPI3_IOUNIT10_FLAGS_ACTIVEID_FIRST_REGION … #define MPI3_IOUNIT10_FLAGS_ACTIVEID_SECOND_REGION … #define MPI3_IOUNIT10_FLAGS_PBLP_EXPECTED … #ifndef MPI3_IOUNIT11_PROFILE_MAX #define MPI3_IOUNIT11_PROFILE_MAX … #endif struct mpi3_iounit11_profile { … }; struct mpi3_io_unit_page11 { … }; #define MPI3_IOUNIT11_PAGEVERSION … #ifndef MPI3_IOUNIT12_BUCKET_MAX #define MPI3_IOUNIT12_BUCKET_MAX … #endif struct mpi3_iounit12_bucket { … }; struct mpi3_io_unit_page12 { … }; #define MPI3_IOUNIT12_PAGEVERSION … #define MPI3_IOUNIT12_FLAGS_NUMPASSES_MASK … #define MPI3_IOUNIT12_FLAGS_NUMPASSES_SHIFT … #define MPI3_IOUNIT12_FLAGS_NUMPASSES_8 … #define MPI3_IOUNIT12_FLAGS_NUMPASSES_16 … #define MPI3_IOUNIT12_FLAGS_NUMPASSES_32 … #define MPI3_IOUNIT12_FLAGS_NUMPASSES_64 … #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_MASK … #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_DISABLED … #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_500US … #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_1MS … #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_2MS … #ifndef MPI3_IOUNIT13_FUNC_MAX #define MPI3_IOUNIT13_FUNC_MAX … #endif struct mpi3_iounit13_allowed_function { … }; #define MPI3_IOUNIT13_FUNCTION_FLAGS_ADMIN_BLOCKED … #define MPI3_IOUNIT13_FUNCTION_FLAGS_OOB_BLOCKED … #define MPI3_IOUNIT13_FUNCTION_FLAGS_CHECK_SUBFUNCTION_ENABLED … struct mpi3_io_unit_page13 { … }; #define MPI3_IOUNIT13_PAGEVERSION … #define MPI3_IOUNIT13_FLAGS_ADMIN_BLOCKED … #define MPI3_IOUNIT13_FLAGS_OOB_BLOCKED … #ifndef MPI3_IOUNIT14_MD_MAX #define MPI3_IOUNIT14_MD_MAX … #endif struct mpi3_iounit14_pagemetadata { … }; #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_OOBWRITE_ALLOWED … #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_HOSTWRITE_ALLOWED … struct mpi3_io_unit_page14 { … }; #define MPI3_IOUNIT14_PAGEVERSION … #define MPI3_IOUNIT14_FLAGS_READONLY … #ifndef MPI3_IOUNIT15_PBD_MAX #define MPI3_IOUNIT15_PBD_MAX … #endif struct mpi3_io_unit_page15 { … }; #define MPI3_IOUNIT15_PAGEVERSION … #define MPI3_IOUNIT15_FLAGS_EPRINIT_INITREQUIRED … #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_MASK … #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_NOT_SUPPORTED … #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITHOUT_POWER_BRAKE_GPIO … #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITH_POWER_BRAKE_GPIO … #define MPI3_IOUNIT15_NUMPOWERBUDGETDATA_POWER_BUDGETING_DISABLED … struct mpi3_ioc_page0 { … }; #define MPI3_IOC0_PAGEVERSION … struct mpi3_ioc_page1 { … }; #define MPI3_IOC1_PAGEVERSION … #ifndef MPI3_IOC2_EVENTMASK_WORDS #define MPI3_IOC2_EVENTMASK_WORDS … #endif struct mpi3_ioc_page2 { … }; #define MPI3_IOC2_PAGEVERSION … #define MPI3_DRIVER_FLAGS_ADMINRAIDPD_BLOCKED … #define MPI3_DRIVER_FLAGS_OOBRAIDPD_BLOCKED … #define MPI3_DRIVER_FLAGS_OOBRAIDVD_BLOCKED … #define MPI3_DRIVER_FLAGS_OOBADVHOSTPD_BLOCKED … #define MPI3_DRIVER_FLAGS_OOBHOSTPD_BLOCKED … struct mpi3_allowed_cmd_scsi { … }; struct mpi3_allowed_cmd_ata { … }; struct mpi3_allowed_cmd_nvme { … }; #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_MASK … #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_IO … #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_ADMIN … #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_MASK … #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_NVM … mpi3_allowed_cmd; #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_ADMINRAIDPD_BLOCKED … #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDPD_BLOCKED … #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDVD_BLOCKED … #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBADVHOSTPD_BLOCKED … #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBHOSTPD_BLOCKED … #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_CHECKSUBCMD_ENABLED … #ifndef MPI3_ALLOWED_CMDS_MAX #define MPI3_ALLOWED_CMDS_MAX … #endif struct mpi3_driver_page0 { … }; #define MPI3_DRIVER0_PAGEVERSION … #define MPI3_DRIVER0_BSDOPTS_DEVICEEXPOSURE_DISABLE … #define MPI3_DRIVER0_BSDOPTS_WRITECACHE_DISABLE … #define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE … #define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL … #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK … #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS … #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY … #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_INTERNAL_DEVS … struct mpi3_driver_page1 { … }; #define MPI3_DRIVER1_PAGEVERSION … #ifndef MPI3_DRIVER2_TRIGGER_MAX #define MPI3_DRIVER2_TRIGGER_MAX … #endif struct mpi3_driver2_trigger_event { … }; struct mpi3_driver2_trigger_scsi_sense { … }; #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASCQ_MATCH_ALL … #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASC_MATCH_ALL … #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_SENSE_KEY_MATCH_ALL … struct mpi3_driver2_trigger_reply { … }; #define MPI3_DRIVER2_TRIGGER_REPLY_IOCSTATUS_MATCH_ALL … mpi3_driver2_trigger_element; #define MPI3_DRIVER2_TRIGGER_TYPE_EVENT … #define MPI3_DRIVER2_TRIGGER_TYPE_SCSI_SENSE … #define MPI3_DRIVER2_TRIGGER_TYPE_REPLY … #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_TRACE_RELEASE … #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_FW_RELEASE … struct mpi3_driver_page2 { … }; #define MPI3_DRIVER2_PAGEVERSION … #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_TRACE_RELEASE … #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_FW_RELEASE … #define MPI3_DRIVER2_GLOBALTRIGGER_SNAPDUMP_ENABLED … #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED … #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED … #define MPI3_DRIVER2_GLOBALTRIGGER_DEVICE_REMOVAL_ENABLED … #define MPI3_DRIVER2_GLOBALTRIGGER_TASK_MANAGEMENT_ENABLED … struct mpi3_driver_page10 { … }; #define MPI3_DRIVER10_PAGEVERSION … struct mpi3_driver_page20 { … }; #define MPI3_DRIVER20_PAGEVERSION … struct mpi3_driver_page30 { … }; #define MPI3_DRIVER30_PAGEVERSION … mpi3_security_mac; mpi3_security_nonce; mpi3_security_root_digest; mpi3_security0_cert_chain; struct mpi3_security_page0 { … }; #define MPI3_SECURITY0_PAGEVERSION … #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_MASK … #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_UNUSED … #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_CERBERUS … #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SPDM … #define MPI3_SECURITY0_CERTCHAIN_FLAGS_SEALED … #ifndef MPI3_SECURITY1_KEY_RECORD_MAX #define MPI3_SECURITY1_KEY_RECORD_MAX … #endif #ifndef MPI3_SECURITY1_PAD_MAX #define MPI3_SECURITY1_PAD_MAX … #endif mpi3_security1_key_data; struct mpi3_security1_key_record { … }; #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_MASK … #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_NOT_VALID … #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_HMAC … #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_AES … #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PRIVATE … #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PUBLIC … #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_NOT_VALID … #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_SAFESTORE … #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CERT_CHAIN … #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_DEVICE_KEY … #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CACHE_OFFLOAD … struct mpi3_security_page1 { … }; #define MPI3_SECURITY1_PAGEVERSION … #ifndef MPI3_SECURITY2_TRUSTED_ROOT_MAX #define MPI3_SECURITY2_TRUSTED_ROOT_MAX … #endif struct mpi3_security2_trusted_root { … }; #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_MASK … #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_SHIFT … #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_HA_FIELD … #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_AKI … #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_USERPROVISIONED_YES … struct mpi3_security_page2 { … }; #define MPI3_SECURITY2_PAGEVERSION … struct mpi3_sas_io_unit0_phy_data { … }; #ifndef MPI3_SAS_IO_UNIT0_PHY_MAX #define MPI3_SAS_IO_UNIT0_PHY_MAX … #endif struct mpi3_sas_io_unit_page0 { … }; #define MPI3_SASIOUNIT0_PAGEVERSION … #define MPI3_SASIOUNIT0_INITSTATUS_NO_ERRORS … #define MPI3_SASIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION … #define MPI3_SASIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED … #define MPI3_SASIOUNIT0_INITSTATUS_BAD_NUM_PHYS … #define MPI3_SASIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG … #define MPI3_SASIOUNIT0_INITSTATUS_HOST_PHYS_ENABLED … #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MIN … #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MAX … #define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS … #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_MASK … #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_IOUNIT1 … #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_DYNAMIC … #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_BACKPLANE … #define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT … #define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT … #define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED … #define MPI3_SASIOUNIT0_PHYFLAGS_VIRTUAL_PHY … #define MPI3_SASIOUNIT0_PHYFLAGS_HOST_PHY … struct mpi3_sas_io_unit1_phy_data { … }; #ifndef MPI3_SAS_IO_UNIT1_PHY_MAX #define MPI3_SAS_IO_UNIT1_PHY_MAX … #endif struct mpi3_sas_io_unit_page1 { … }; #define MPI3_SASIOUNIT1_PAGEVERSION … #define MPI3_SASIOUNIT1_CONTROL_CONTROLLER_DEVICE_SELF_TEST … #define MPI3_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE … #define MPI3_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED … #define MPI3_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED … #define MPI3_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED … #define MPI3_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED … #define MPI3_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL … #define MPI3_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL … #define MPI3_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY … #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_MASK … #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_DEVICE_NAME … #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SAS_ADDRESS … #define MPI3_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT … #define MPI3_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL … #define MPI3_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION … #define MPI3_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION … #define MPI3_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET … #define MPI3_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET … #define MPI3_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET … #define MPI3_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET … #define MPI3_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE … #define MPI3_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG … #define MPI3_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT … #define MPI3_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT … #define MPI3_SASIOUNIT1_PHYFLAGS_PHY_DISABLE … #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_MASK … #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_SHIFT … #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_6_0 … #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_12_0 … #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_22_5 … #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_MASK … #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_6_0 … #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_12_0 … #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_22_5 … struct mpi3_sas_io_unit2_phy_pm_settings { … }; #ifndef MPI3_SAS_IO_UNIT2_PHY_MAX #define MPI3_SAS_IO_UNIT2_PHY_MAX … #endif struct mpi3_sas_io_unit_page2 { … }; #define MPI3_SASIOUNIT2_PAGEVERSION … #define MPI3_SASIOUNIT2_CONTROL_SAS_SLUMBER_ENABLE … #define MPI3_SASIOUNIT2_CONTROL_SAS_PARTIAL_ENABLE … #define MPI3_SASIOUNIT2_CONTROL_SATA_SLUMBER_ENABLE … #define MPI3_SASIOUNIT2_CONTROL_SATA_PARTIAL_ENABLE … #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_MASK … #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_SHIFT … #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_MASK … #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_SHIFT … #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_MASK … #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_SHIFT … #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_MASK … #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_SHIFT … #define MPI3_SASIOUNIT2_ITE_EXP_TEN_SECONDS … #define MPI3_SASIOUNIT2_ITE_EXP_ONE_SECOND … #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MILLISECONDS … #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MILLISECONDS … #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MILLISECOND … #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MICROSECONDS … #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MICROSECONDS … #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MICROSECOND … struct mpi3_sas_io_unit_page3 { … }; #define MPI3_SASIOUNIT3_PAGEVERSION … #define MPI3_SASIOUNIT3_PM_HOST_SAS_SLUMBER_MODE … #define MPI3_SASIOUNIT3_PM_HOST_SAS_PARTIAL_MODE … #define MPI3_SASIOUNIT3_PM_HOST_SATA_SLUMBER_MODE … #define MPI3_SASIOUNIT3_PM_HOST_SATA_PARTIAL_MODE … #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_SLUMBER_MODE … #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_PARTIAL_MODE … #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_SLUMBER_MODE … #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_PARTIAL_MODE … struct mpi3_sas_expander_page0 { … }; #define MPI3_SASEXPANDER0_PAGEVERSION … #define MPI3_SASEXPANDER0_FLAGS_REDUCED_FUNCTIONALITY … #define MPI3_SASEXPANDER0_FLAGS_ZONE_LOCKED … #define MPI3_SASEXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES … #define MPI3_SASEXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES … #define MPI3_SASEXPANDER0_FLAGS_ZONING_SUPPORT … #define MPI3_SASEXPANDER0_FLAGS_ENABLED_ZONING … #define MPI3_SASEXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT … #define MPI3_SASEXPANDER0_FLAGS_CONNECTOR_END_DEVICE … #define MPI3_SASEXPANDER0_FLAGS_OTHERS_CONFIG … #define MPI3_SASEXPANDER0_FLAGS_CONFIG_IN_PROGRESS … #define MPI3_SASEXPANDER0_FLAGS_ROUTE_TABLE_CONFIG … #define MPI3_SASEXPANDER0_ES_NOT_RESPONDING … #define MPI3_SASEXPANDER0_ES_RESPONDING … #define MPI3_SASEXPANDER0_ES_DELAY_NOT_RESPONDING … struct mpi3_sas_expander_page1 { … }; #define MPI3_SASEXPANDER1_PAGEVERSION … #define MPI3_SASEXPANDER1_DISCINFO_BAD_PHY_DISABLED … #define MPI3_SASEXPANDER1_DISCINFO_LINK_STATUS_CHANGE … #define MPI3_SASEXPANDER1_DISCINFO_NO_ROUTING_ENTRIES … #ifndef MPI3_SASEXPANDER2_MAX_NUM_PHYS #define MPI3_SASEXPANDER2_MAX_NUM_PHYS … #endif struct mpi3_sasexpander2_phy_element { … }; struct mpi3_sas_expander_page2 { … }; #define MPI3_SASEXPANDER2_PAGEVERSION … struct mpi3_sas_port_page0 { … }; #define MPI3_SASPORT0_PAGEVERSION … struct mpi3_sas_phy_page0 { … }; #define MPI3_SASPHY0_PAGEVERSION … #define MPI3_SASPHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC … struct mpi3_sas_phy_page1 { … }; #define MPI3_SASPHY1_PAGEVERSION … struct mpi3_sas_phy2_phy_event { … }; #ifndef MPI3_SAS_PHY2_PHY_EVENT_MAX #define MPI3_SAS_PHY2_PHY_EVENT_MAX … #endif struct mpi3_sas_phy_page2 { … }; #define MPI3_SASPHY2_PAGEVERSION … struct mpi3_sas_phy3_phy_event_config { … }; #define MPI3_SASPHY3_EVENT_CODE_NO_EVENT … #define MPI3_SASPHY3_EVENT_CODE_INVALID_DWORD … #define MPI3_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR … #define MPI3_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC … #define MPI3_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM … #define MPI3_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW … #define MPI3_SASPHY3_EVENT_CODE_RX_ERROR … #define MPI3_SASPHY3_EVENT_CODE_INV_SPL_PACKETS … #define MPI3_SASPHY3_EVENT_CODE_LOSS_SPL_PACKET_SYNC … #define MPI3_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR … #define MPI3_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT … #define MPI3_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT … #define MPI3_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT … #define MPI3_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT … #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON … #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON … #define MPI3_SASPHY3_EVENT_CODE_TX_BREAK … #define MPI3_SASPHY3_EVENT_CODE_RX_BREAK … #define MPI3_SASPHY3_EVENT_CODE_BREAK_TIMEOUT … #define MPI3_SASPHY3_EVENT_CODE_CONNECTION … #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED … #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME … #define MPI3_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME … #define MPI3_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME … #define MPI3_SASPHY3_EVENT_CODE_PERSIST_CONN … #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_FRAMES … #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_FRAMES … #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES … #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES … #define MPI3_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED … #define MPI3_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED … #define MPI3_SASPHY3_EVENT_CODE_TX_SATA_FRAMES … #define MPI3_SASPHY3_EVENT_CODE_RX_SATA_FRAMES … #define MPI3_SASPHY3_EVENT_CODE_SATA_OVERFLOW … #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_FRAMES … #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_FRAMES … #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES … #define MPI3_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT … #define MPI3_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE … #define MPI3_SASPHY3_EVENT_CODE_RX_AIP … #define MPI3_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME … #define MPI3_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME … #define MPI3_SASPHY3_EVENT_CODE_LCCONN_TIME … #define MPI3_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT … #define MPI3_SASPHY3_EVENT_CODE_SATA_TX_START … #define MPI3_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT … #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN … #define MPI3_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE … #define MPI3_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE … #define MPI3_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE … #define MPI3_SASPHY3_COUNTER_TYPE_WRAPPING … #define MPI3_SASPHY3_COUNTER_TYPE_SATURATING … #define MPI3_SASPHY3_COUNTER_TYPE_PEAK_VALUE … #define MPI3_SASPHY3_TIME_UNITS_10_MICROSECONDS … #define MPI3_SASPHY3_TIME_UNITS_100_MICROSECONDS … #define MPI3_SASPHY3_TIME_UNITS_1_MILLISECOND … #define MPI3_SASPHY3_TIME_UNITS_10_MILLISECONDS … #define MPI3_SASPHY3_TFLAGS_PHY_RESET … #define MPI3_SASPHY3_TFLAGS_EVENT_NOTIFY … #ifndef MPI3_SAS_PHY3_PHY_EVENT_MAX #define MPI3_SAS_PHY3_PHY_EVENT_MAX … #endif struct mpi3_sas_phy_page3 { … }; #define MPI3_SASPHY3_PAGEVERSION … struct mpi3_sas_phy_page4 { … }; #define MPI3_SASPHY4_PAGEVERSION … #define MPI3_SASPHY4_FLAGS_FRAME_VALID … #define MPI3_SASPHY4_FLAGS_SATA_FRAME … #define MPI3_PCIE_LINK_RETIMERS_MASK … #define MPI3_PCIE_LINK_RETIMERS_SHIFT … #define MPI3_PCIE_NEG_LINK_RATE_MASK … #define MPI3_PCIE_NEG_LINK_RATE_UNKNOWN … #define MPI3_PCIE_NEG_LINK_RATE_PHY_DISABLED … #define MPI3_PCIE_NEG_LINK_RATE_2_5 … #define MPI3_PCIE_NEG_LINK_RATE_5_0 … #define MPI3_PCIE_NEG_LINK_RATE_8_0 … #define MPI3_PCIE_NEG_LINK_RATE_16_0 … #define MPI3_PCIE_NEG_LINK_RATE_32_0 … #define MPI3_PCIE_ASPM_ENABLE_NONE … #define MPI3_PCIE_ASPM_ENABLE_L0S … #define MPI3_PCIE_ASPM_ENABLE_L1 … #define MPI3_PCIE_ASPM_ENABLE_L0S_L1 … #define MPI3_PCIE_ASPM_SUPPORT_NONE … #define MPI3_PCIE_ASPM_SUPPORT_L0S … #define MPI3_PCIE_ASPM_SUPPORT_L1 … #define MPI3_PCIE_ASPM_SUPPORT_L0S_L1 … struct mpi3_pcie_io_unit0_phy_data { … }; #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_MASK … #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_IOUNIT1 … #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_BKPLANE … #define MPI3_PCIEIOUNIT0_LINKFLAGS_ENUM_IN_PROGRESS … #define MPI3_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED … #define MPI3_PCIEIOUNIT0_PHYFLAGS_HOST_PHY … #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCH_DEPTH_EXCEEDED … #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED … #define MPI3_PCIEIOUNIT0_ES_MAX_ENDPOINTS_EXCEEDED … #define MPI3_PCIEIOUNIT0_ES_INSUFFICIENT_RESOURCES … #ifndef MPI3_PCIE_IO_UNIT0_PHY_MAX #define MPI3_PCIE_IO_UNIT0_PHY_MAX … #endif struct mpi3_pcie_io_unit_page0 { … }; #define MPI3_PCIEIOUNIT0_PAGEVERSION … #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_ERRORS … #define MPI3_PCIEIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION … #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED … #define MPI3_PCIEIOUNIT0_INITSTATUS_RESOURCE_ALLOC_FAILED … #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_NUM_PHYS … #define MPI3_PCIEIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG … #define MPI3_PCIEIOUNIT0_INITSTATUS_HOST_PORT_MISMATCH … #define MPI3_PCIEIOUNIT0_INITSTATUS_PHYS_NOT_CONSECUTIVE … #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_CLOCKING_MODE … #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_START … #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_END … #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_MASK … #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_SHIFT … #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_MASK … #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_SHIFT … #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_MASK … #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_SHIFT … #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_MASK … #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_SHIFT … struct mpi3_pcie_io_unit1_phy_data { … }; #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_MASK … #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK … #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS … #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS … #define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE … #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK … #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT … #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5 … #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0 … #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0 … #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0 … #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0 … #ifndef MPI3_PCIE_IO_UNIT1_PHY_MAX #define MPI3_PCIE_IO_UNIT1_PHY_MAX … #endif struct mpi3_pcie_io_unit_page1 { … }; #define MPI3_PCIEIOUNIT1_PAGEVERSION … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_MASK … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_NONE … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_DEASSERT … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_ASSERT … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_BACKPLANE_ERROR … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_MASK … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_NONE … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_DEASSERT … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_ASSERT … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_BACKPLANE_ERROR … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SHIFT … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_USE_BACKPLANE … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5 … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0 … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0 … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0 … #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0 … #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_MASK … #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_SHIFT … #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_MASK … #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_SHIFT … struct mpi3_pcie_io_unit_page2 { … }; #define MPI3_PCIEIOUNIT2_PAGEVERSION … #define MPI3_PCIEIOUNIT3_ERROR_RECEIVER_ERROR … #define MPI3_PCIEIOUNIT3_ERROR_RECOVERY … #define MPI3_PCIEIOUNIT3_ERROR_CORRECTABLE_ERROR_MSG … #define MPI3_PCIEIOUNIT3_ERROR_BAD_DLLP … #define MPI3_PCIEIOUNIT3_ERROR_BAD_TLP … #define MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX … struct mpi3_pcie_io_unit3_error { … }; struct mpi3_pcie_io_unit_page3 { … }; #define MPI3_PCIEIOUNIT3_PAGEVERSION … #define MPI3_PCIEIOUNIT3_ACTION_NO_ACTION … #define MPI3_PCIEIOUNIT3_ACTION_HOT_RESET … #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_ONLY … #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_NO_ACCESS … struct mpi3_pcie_switch_page0 { … }; #define MPI3_PCIESWITCH0_PAGEVERSION … #define MPI3_PCIESWITCH0_SS_NOT_RESPONDING … #define MPI3_PCIESWITCH0_SS_RESPONDING … #define MPI3_PCIESWITCH0_SS_DELAY_NOT_RESPONDING … struct mpi3_pcie_switch_page1 { … }; #define MPI3_PCIESWITCH1_PAGEVERSION … #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_MASK … #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_SHIFT … #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_MASK … #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_SHIFT … #ifndef MPI3_PCIESWITCH2_MAX_NUM_PORTS #define MPI3_PCIESWITCH2_MAX_NUM_PORTS … #endif struct mpi3_pcieswitch2_port_element { … }; struct mpi3_pcie_switch_page2 { … }; #define MPI3_PCIESWITCH2_PAGEVERSION … struct mpi3_pcie_link_page0 { … }; #define MPI3_PCIELINK0_PAGEVERSION … struct mpi3_enclosure_page0 { … }; #define MPI3_ENCLOSURE0_PAGEVERSION … #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_MASK … #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL … #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS … #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE … #define MPI3_ENCLS0_FLAGS_CHASSIS_SLOT_VALID … #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK … #define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND … #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT … #define MPI3_ENCLS0_FLAGS_MNG_MASK … #define MPI3_ENCLS0_FLAGS_MNG_UNKNOWN … #define MPI3_ENCLS0_FLAGS_MNG_IOC_SES … #define MPI3_ENCLS0_FLAGS_MNG_SES_ENCLOSURE … #define MPI3_DEVICE_DEVFORM_SAS_SATA … #define MPI3_DEVICE_DEVFORM_PCIE … #define MPI3_DEVICE_DEVFORM_VD … struct mpi3_device0_sas_sata_format { … }; #define MPI3_DEVICE0_SASSATA_FLAGS_WRITE_SAME_UNMAP_NCQ … #define MPI3_DEVICE0_SASSATA_FLAGS_SLUMBER_CAP … #define MPI3_DEVICE0_SASSATA_FLAGS_PARTIAL_CAP … #define MPI3_DEVICE0_SASSATA_FLAGS_ASYNC_NOTIFY … #define MPI3_DEVICE0_SASSATA_FLAGS_SW_PRESERVE … #define MPI3_DEVICE0_SASSATA_FLAGS_UNSUPP_DEV … #define MPI3_DEVICE0_SASSATA_FLAGS_48BIT_LBA … #define MPI3_DEVICE0_SASSATA_FLAGS_SMART_SUPP … #define MPI3_DEVICE0_SASSATA_FLAGS_NCQ_SUPP … #define MPI3_DEVICE0_SASSATA_FLAGS_FUA_SUPP … #define MPI3_DEVICE0_SASSATA_FLAGS_PERSIST_CAP … struct mpi3_device0_pcie_format { … }; #define MPI3_DEVICE0_PCIE_LINK_RATE_32_0_SUPP … #define MPI3_DEVICE0_PCIE_LINK_RATE_16_0_SUPP … #define MPI3_DEVICE0_PCIE_LINK_RATE_8_0_SUPP … #define MPI3_DEVICE0_PCIE_LINK_RATE_5_0_SUPP … #define MPI3_DEVICE0_PCIE_LINK_RATE_2_5_SUPP … #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK … #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE … #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE … #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE … #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE … #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_MASK … #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_SHIFT … #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_MASK … #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_SHIFT … #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_0 … #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_1 … #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_2 … #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_3 … #define MPI3_DEVICE0_PCIE_CAP_SGL_EXTRA_LENGTH_SUPPORTED … #define MPI3_DEVICE0_PCIE_CAP_METADATA_SEPARATED … #define MPI3_DEVICE0_PCIE_CAP_SGL_DWORD_ALIGN_REQUIRED … #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_SGL … #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_PRP … #define MPI3_DEVICE0_PCIE_CAP_BIT_BUCKET_SGL_SUPP … #define MPI3_DEVICE0_PCIE_CAP_SGL_SUPP … #define MPI3_DEVICE0_PCIE_CAP_ASPM_MASK … #define MPI3_DEVICE0_PCIE_CAP_ASPM_SHIFT … #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_MASK … #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_NS_MGMT … #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_FORMAT … #define MPI3_DEVICE0_PCIE_RECOVER_REASON_MASK … #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NS … #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NSID_1 … #define MPI3_DEVICE0_PCIE_RECOVER_REASON_TOO_MANY_NS … #define MPI3_DEVICE0_PCIE_RECOVER_REASON_PROTECTION … #define MPI3_DEVICE0_PCIE_RECOVER_REASON_METADATA_SZ … #define MPI3_DEVICE0_PCIE_RECOVER_REASON_LBA_DATA_SZ … struct mpi3_device0_vd_format { … }; #define MPI3_DEVICE0_VD_STATE_OFFLINE … #define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED … #define MPI3_DEVICE0_VD_STATE_DEGRADED … #define MPI3_DEVICE0_VD_STATE_OPTIMAL … #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_0 … #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_1 … #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_5 … #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_6 … #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_10 … #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_50 … #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_60 … #define MPI3_DEVICE0_VD_DEVICE_INFO_HDD … #define MPI3_DEVICE0_VD_DEVICE_INFO_SSD … #define MPI3_DEVICE0_VD_DEVICE_INFO_NVME … #define MPI3_DEVICE0_VD_DEVICE_INFO_SATA … #define MPI3_DEVICE0_VD_DEVICE_INFO_SAS … #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_MASK … #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_SHIFT … mpi3_device0_dev_spec_format; struct mpi3_device_page0 { … }; #define MPI3_DEVICE0_PAGEVERSION … #define MPI3_DEVICE0_PARENT_INVALID … #define MPI3_DEVICE0_ENCLOSURE_HANDLE_NO_ENCLOSURE … #define MPI3_DEVICE0_WWID_INVALID … #define MPI3_DEVICE0_PERSISTENTID_INVALID … #define MPI3_DEVICE0_IOUNITPORT_INVALID … #define MPI3_DEVICE0_ASTATUS_NO_ERRORS … #define MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION … #define MPI3_DEVICE0_ASTATUS_CAP_UNSUPPORTED … #define MPI3_DEVICE0_ASTATUS_DEVICE_BLOCKED … #define MPI3_DEVICE0_ASTATUS_UNAUTHORIZED … #define MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY … #define MPI3_DEVICE0_ASTATUS_PREPARE … #define MPI3_DEVICE0_ASTATUS_SAFE_MODE … #define MPI3_DEVICE0_ASTATUS_GENERIC_MAX … #define MPI3_DEVICE0_ASTATUS_SAS_UNKNOWN … #define MPI3_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE … #define MPI3_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE … #define MPI3_DEVICE0_ASTATUS_SAS_MAX … #define MPI3_DEVICE0_ASTATUS_SIF_UNKNOWN … #define MPI3_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT … #define MPI3_DEVICE0_ASTATUS_SIF_DIAG … #define MPI3_DEVICE0_ASTATUS_SIF_IDENTIFICATION … #define MPI3_DEVICE0_ASTATUS_SIF_CHECK_POWER … #define MPI3_DEVICE0_ASTATUS_SIF_PIO_SN … #define MPI3_DEVICE0_ASTATUS_SIF_MDMA_SN … #define MPI3_DEVICE0_ASTATUS_SIF_UDMA_SN … #define MPI3_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION … #define MPI3_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE … #define MPI3_DEVICE0_ASTATUS_SIF_MAX … #define MPI3_DEVICE0_ASTATUS_PCIE_UNKNOWN … #define MPI3_DEVICE0_ASTATUS_PCIE_MEM_SPACE_ACCESS … #define MPI3_DEVICE0_ASTATUS_PCIE_UNSUPPORTED … #define MPI3_DEVICE0_ASTATUS_PCIE_MSIX_REQUIRED … #define MPI3_DEVICE0_ASTATUS_PCIE_ECRC_REQUIRED … #define MPI3_DEVICE0_ASTATUS_PCIE_MAX … #define MPI3_DEVICE0_ASTATUS_NVME_UNKNOWN … #define MPI3_DEVICE0_ASTATUS_NVME_READY_TIMEOUT … #define MPI3_DEVICE0_ASTATUS_NVME_DEVCFG_UNSUPPORTED … #define MPI3_DEVICE0_ASTATUS_NVME_IDENTIFY_FAILED … #define MPI3_DEVICE0_ASTATUS_NVME_QCONFIG_FAILED … #define MPI3_DEVICE0_ASTATUS_NVME_QCREATION_FAILED … #define MPI3_DEVICE0_ASTATUS_NVME_EVENTCFG_FAILED … #define MPI3_DEVICE0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED … #define MPI3_DEVICE0_ASTATUS_NVME_IDLE_TIMEOUT … #define MPI3_DEVICE0_ASTATUS_NVME_CTRL_FAILURE_STATUS … #define MPI3_DEVICE0_ASTATUS_NVME_INSUFFICIENT_POWER … #define MPI3_DEVICE0_ASTATUS_NVME_DOORBELL_STRIDE … #define MPI3_DEVICE0_ASTATUS_NVME_MEM_PAGE_MIN_SIZE … #define MPI3_DEVICE0_ASTATUS_NVME_MEMORY_ALLOCATION … #define MPI3_DEVICE0_ASTATUS_NVME_COMPLETION_TIME … #define MPI3_DEVICE0_ASTATUS_NVME_BAR … #define MPI3_DEVICE0_ASTATUS_NVME_NS_DESCRIPTOR … #define MPI3_DEVICE0_ASTATUS_NVME_INCOMPATIBLE_SETTINGS … #define MPI3_DEVICE0_ASTATUS_NVME_TOO_MANY_ERRORS … #define MPI3_DEVICE0_ASTATUS_NVME_MAX … #define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN … #define MPI3_DEVICE0_ASTATUS_VD_MAX … #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_MASK … #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_NO_LIMIT … #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_256_LB … #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_2048_LB … #define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE … #define MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED … #define MPI3_DEVICE0_FLAGS_HIDDEN … #define MPI3_DEVICE0_FLAGS_ATT_METHOD_VIRTUAL … #define MPI3_DEVICE0_FLAGS_ATT_METHOD_DIR_ATTACHED … #define MPI3_DEVICE0_FLAGS_DEVICE_PRESENT … #define MPI3_DEVICE0_QUEUE_DEPTH_NOT_APPLICABLE … struct mpi3_device1_sas_sata_format { … }; struct mpi3_device1_pcie_format { … }; #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_128B … #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_256B … #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_512B … #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_1024B … #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_2048B … #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_4096B … #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_MASK … #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_SHIFT … #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_MASK … #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_SHIFT … #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_MASK … #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_SHIFT … struct mpi3_device1_vd_format { … }; mpi3_device1_dev_spec_format; struct mpi3_device_page1 { … }; #define MPI3_DEVICE1_PAGEVERSION … #define MPI3_DEVICE1_COUNTER_MAX … #define MPI3_DEVICE1_COUNTER_INVALID … #endif
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