// SPDX-License-Identifier: GPL-2.0-only /* * linux/arch/arm/plat-pxa/gpio.c * * Generic PXA GPIO handling * * Author: Nicolas Pitre * Created: Jun 15, 2001 * Copyright: MontaVista Software Inc. */ #include <linux/module.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/gpio/driver.h> #include <linux/gpio-pxa.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/irqdomain.h> #include <linux/irqchip/chained_irq.h> #include <linux/io.h> #include <linux/of.h> #include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> #include <linux/syscore_ops.h> #include <linux/slab.h> /* * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with * one set of registers. The register offsets are organized below: * * GPLR GPDR GPSR GPCR GRER GFER GEDR * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 * * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 * * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248 * * NOTE: * BANK 3 is only available on PXA27x and later processors. * BANK 4 and 5 are only available on PXA935, PXA1928 * BANK 6 is only available on PXA1928 */ #define GPLR_OFFSET … #define GPDR_OFFSET … #define GPSR_OFFSET … #define GPCR_OFFSET … #define GRER_OFFSET … #define GFER_OFFSET … #define GEDR_OFFSET … #define GAFR_OFFSET … #define ED_MASK_OFFSET … #define BANK_OFF(n) … int pxa_last_gpio; static int irq_base; struct pxa_gpio_bank { … }; struct pxa_gpio_chip { … }; enum pxa_gpio_type { … }; struct pxa_gpio_id { … }; static DEFINE_SPINLOCK(gpio_lock); static struct pxa_gpio_chip *pxa_gpio_chip; static enum pxa_gpio_type gpio_type; static struct pxa_gpio_id pxa25x_id = …; static struct pxa_gpio_id pxa26x_id = …; static struct pxa_gpio_id pxa27x_id = …; static struct pxa_gpio_id pxa3xx_id = …; static struct pxa_gpio_id pxa93x_id = …; static struct pxa_gpio_id mmp_id = …; static struct pxa_gpio_id mmp2_id = …; static struct pxa_gpio_id pxa1928_id = …; #define for_each_gpio_bank(i, b, pc) … static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c) { … } static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio) { … } static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c, unsigned gpio) { … } static inline int gpio_is_mmp_type(int type) { … } /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, * as well as their Alternate Function value being '1' for GPIO in GAFRx. */ static inline int __gpio_is_inverted(int gpio) { … } /* * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate * function of a GPIO, and GPDRx cannot be altered once configured. It * is attributed as "occupied" here (I know this terminology isn't * accurate, you are welcome to propose a better one :-) */ static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio) { … } int pxa_irq_to_gpio(int irq) { … } static bool pxa_gpio_has_pinctrl(void) { … } static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) { … } static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { … } static int pxa_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { … } static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) { … } static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { … } #ifdef CONFIG_OF_GPIO static int pxa_gpio_of_xlate(struct gpio_chip *gc, const struct of_phandle_args *gpiospec, u32 *flags) { … } #endif static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, void __iomem *regbase) { … } /* Update only those GRERx and GFERx edge detection register bits if those * bits are set in c->irq_mask */ static inline void update_edge_detect(struct pxa_gpio_bank *c) { … } static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) { … } static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d) { … } static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d) { … } static void pxa_ack_muxed_gpio(struct irq_data *d) { … } static void pxa_mask_muxed_gpio(struct irq_data *d) { … } static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) { … } static void pxa_unmask_muxed_gpio(struct irq_data *d) { … } static struct irq_chip pxa_muxed_gpio_chip = …; static int pxa_gpio_nums(struct platform_device *pdev) { … } static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { … } static const struct irq_domain_ops pxa_irq_domain_ops = …; #ifdef CONFIG_OF static const struct of_device_id pxa_gpio_dt_ids[] = …; static int pxa_gpio_probe_dt(struct platform_device *pdev, struct pxa_gpio_chip *pchip) { … } #else #define pxa_gpio_probe_dt … #endif static int pxa_gpio_probe(struct platform_device *pdev) { … } static const struct platform_device_id gpio_id_table[] = …; static struct platform_driver pxa_gpio_driver = …; static int __init pxa_gpio_legacy_init(void) { … } postcore_initcall(pxa_gpio_legacy_init); static int __init pxa_gpio_dt_init(void) { … } device_initcall(pxa_gpio_dt_init); #ifdef CONFIG_PM static int pxa_gpio_suspend(void) { … } static void pxa_gpio_resume(void) { … } #else #define pxa_gpio_suspend … #define pxa_gpio_resume … #endif static struct syscore_ops pxa_gpio_syscore_ops = …; static int __init pxa_gpio_sysinit(void) { … } postcore_initcall(pxa_gpio_sysinit);
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