/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright 2017 Broadcom. All Rights Reserved. * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. * * Contact Information: * [email protected] */ #ifndef _BEISCSI_MAIN_ #define _BEISCSI_MAIN_ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/if_ether.h> #include <linux/in.h> #include <linux/ctype.h> #include <linux/module.h> #include <scsi/scsi.h> #include <scsi/scsi_cmnd.h> #include <scsi/scsi_device.h> #include <scsi/scsi_host.h> #include <scsi/iscsi_proto.h> #include <scsi/libiscsi.h> #include <scsi/scsi_transport_iscsi.h> #define DRV_NAME … #define BUILD_STR … #define BE_NAME … #define DRV_DESC … #define BE_VENDOR_ID … #define ELX_VENDOR_ID … /* DEVICE ID's for BE2 */ #define BE_DEVICE_ID1 … #define OC_DEVICE_ID1 … #define OC_DEVICE_ID2 … /* DEVICE ID's for BE3 */ #define BE_DEVICE_ID2 … #define OC_DEVICE_ID3 … /* DEVICE ID for SKH */ #define OC_SKH_ID1 … #define BE2_IO_DEPTH … #define BE2_MAX_SESSIONS … #define BE2_TMFS … #define BE2_NOPOUT_REQ … #define BE2_SGE … #define BE2_DEFPDU_HDR_SZ … #define BE2_DEFPDU_DATA_SZ … #define BE2_MAX_NUM_CQ_PROC … #define MAX_CPUS … #define BEISCSI_MAX_NUM_CPUS … #define BEISCSI_VER_STRLEN … #define BEISCSI_SGLIST_ELEMENTS … /** * BE_INVLDT_CMD_TBL_SZ is 128 which is total number commands that can * be invalidated at a time, consider it before changing the value of * BEISCSI_CMD_PER_LUN. */ #define BEISCSI_CMD_PER_LUN … #define BEISCSI_MAX_SECTORS … #define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE … #define BEISCSI_MAX_CMD_LEN … #define BEISCSI_NUM_MAX_LUN … #define BEISCSI_MAX_FRAGS_INIT … #define BE_SENSE_INFO_SIZE … #define BE_ISCSI_PDU_HEADER_SIZE … #define BE_MIN_MEM_SIZE … #define MAX_CMD_SZ … #define IIOC_SCSI_DATA … /** * hardware needs the async PDU buffers to be posted in multiples of 8 * So have atleast 8 of them by default */ #define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num) … /********* Memory BAR register ************/ #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET … /** * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt * Disable" may still globally block interrupts in addition to individual * interrupt masks; a mechanism for the device driver to block all interrupts * atomically without having to arbitrate for the PCI Interrupt Disable bit * with the OS. */ #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK … /********* ISR0 Register offset **********/ #define CEV_ISR0_OFFSET … #define CEV_ISR_SIZE … /** * Macros for reading/writing a protection domain or CSR registers * in BladeEngine. */ #define DB_TXULP0_OFFSET … #define DB_RXULP0_OFFSET … /********* Event Q door bell *************/ #define DB_EQ_OFFSET … #define DB_EQ_RING_ID_LOW_MASK … /* Clear the interrupt for this eq */ #define DB_EQ_CLR_SHIFT … /* Must be 1 */ #define DB_EQ_EVNT_SHIFT … /* Higher Order EQ_ID bit */ #define DB_EQ_RING_ID_HIGH_MASK … #define DB_EQ_HIGH_SET_SHIFT … #define DB_EQ_HIGH_FEILD_SHIFT … /* Number of event entries processed */ #define DB_EQ_NUM_POPPED_SHIFT … /* Rearm bit */ #define DB_EQ_REARM_SHIFT … /********* Compl Q door bell *************/ #define DB_CQ_OFFSET … #define DB_CQ_RING_ID_LOW_MASK … /* Higher Order CQ_ID bit */ #define DB_CQ_RING_ID_HIGH_MASK … #define DB_CQ_HIGH_SET_SHIFT … #define DB_CQ_HIGH_FEILD_SHIFT … /* Number of event entries processed */ #define DB_CQ_NUM_POPPED_SHIFT … /* Rearm bit */ #define DB_CQ_REARM_SHIFT … #define GET_HWI_CONTROLLER_WS(pc) … #define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) … #define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) … #define PAGES_REQUIRED(x) … #define MEM_DESCR_OFFSET … #define BEISCSI_DEFQ_HDR … #define BEISCSI_DEFQ_DATA … enum be_mem_enum { … }; struct be_bus_address32 { … }; struct be_bus_address64 { … }; struct be_bus_address { … }; struct mem_array { … }; struct be_mem_descriptor { … }; struct sgl_handle { … }; struct hba_parameters { … }; #define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) … struct hwi_wrb_context { … }; struct ulp_cid_info { … }; #include "be.h" #define chip_be2(phba) … #define chip_be3_r(phba) … #define is_chip_be2_be3r(phba) … #define BEISCSI_ULP0 … #define BEISCSI_ULP1 … #define BEISCSI_ULP_COUNT … #define BEISCSI_ULP0_LOADED … #define BEISCSI_ULP1_LOADED … #define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) … #define BEISCSI_ULP0_AVLBL_CID(phba) … #define BEISCSI_ULP1_AVLBL_CID(phba) … struct beiscsi_hba { … }; #define beiscsi_hba_in_error(phba) … #define beiscsi_hba_is_online(phba) … struct beiscsi_session { … }; /** * struct beiscsi_conn - iscsi connection structure */ struct beiscsi_conn { … }; /* This structure is used by the chip */ struct pdu_data_out { … }; /** * Pseudo amap definition in which each bit of the actual structure is defined * as a byte: used to calculate offset/shift/mask of each field */ struct amap_pdu_data_out { … }; struct be_cmd_bhs { … }; struct beiscsi_io_task { … }; struct be_nonio_bhs { … }; struct be_status_bhs { … }; struct iscsi_sge { … }; /** * Pseudo amap definition in which each bit of the actual structure is defined * as a byte: used to calculate offset/shift/mask of each field */ struct amap_iscsi_sge { … }; struct beiscsi_offload_params { … }; #define OFFLD_PARAMS_ERL … #define OFFLD_PARAMS_DDE … #define OFFLD_PARAMS_HDE … #define OFFLD_PARAMS_IR2T … #define OFFLD_PARAMS_IMD … #define OFFLD_PARAMS_DATA_SEQ_INORDER … #define OFFLD_PARAMS_PDU_SEQ_INORDER … #define OFFLD_PARAMS_MAX_R2T … /** * Pseudo amap definition in which each bit of the actual structure is defined * as a byte: used to calculate offset/shift/mask of each field */ struct amap_beiscsi_offload_params { … }; struct hd_async_handle { … }; #define BEISCSI_ASYNC_HDQ_SIZE(phba, ulp) … /** * This has list of async PDUs that are waiting to be processed. * Buffers live in this list for a brief duration before they get * processed and posted back to hardware. * Note that we don't really need one cri_wait_queue per async_entry. * We need one cri_wait_queue per CRI. Its easier to manage if this * is tagged along with the async_entry. */ struct hd_async_entry { … }; struct hd_async_buf_context { … }; /** * hd_async_context is declared for each ULP supporting iSCSI function. */ struct hd_async_context { … }; struct i_t_dpdu_cqe { … } __packed; /** * Pseudo amap definition in which each bit of the actual structure is defined * as a byte: used to calculate offset/shift/mask of each field */ struct amap_i_t_dpdu_cqe { … } __packed; struct amap_i_t_dpdu_cqe_v2 { … } __packed; #define CQE_VALID_MASK … #define CQE_CODE_MASK … #define CQE_CID_MASK … #define EQE_VALID_MASK … #define EQE_MAJORCODE_MASK … #define EQE_RESID_MASK … struct be_eq_entry { … } __packed; /** * Pseudo amap definition in which each bit of the actual structure is defined * as a byte: used to calculate offset/shift/mask of each field */ struct amap_eq_entry { … } __packed; struct cq_db { … } __packed; /** * Pseudo amap definition in which each bit of the actual structure is defined * as a byte: used to calculate offset/shift/mask of each field */ struct amap_cq_db { … } __packed; void beiscsi_process_eq(struct beiscsi_hba *phba); struct iscsi_wrb { … } __packed; #define WRB_TYPE_MASK … #define SKH_WRB_TYPE_OFFSET … #define BE_WRB_TYPE_OFFSET … #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) … /** * Pseudo amap definition in which each bit of the actual structure is defined * as a byte: used to calculate offset/shift/mask of each field */ struct amap_iscsi_wrb { … } __packed; struct amap_iscsi_wrb_v2 { … } __packed; struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid, struct hwi_wrb_context **pcontext); void free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle); void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn, struct iscsi_task *task); void hwi_ring_cq_db(struct beiscsi_hba *phba, unsigned int id, unsigned int num_processed, unsigned char rearm); unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget); void beiscsi_process_mcc_cq(struct beiscsi_hba *phba); struct pdu_nop_out { … }; /** * Pseudo amap definition in which each bit of the actual structure is defined * as a byte: used to calculate offset/shift/mask of each field */ struct amap_pdu_nop_out { … }; #define PDUBASE_OPCODE_MASK … #define PDUBASE_DATALENHI_MASK … #define PDUBASE_DATALENLO_MASK … struct pdu_base { … } __packed; /** * Pseudo amap definition in which each bit of the actual structure is defined * as a byte: used to calculate offset/shift/mask of each field */ struct amap_pdu_base { … }; struct iscsi_target_context_update_wrb { … } __packed; /** * Pseudo amap definition in which each bit of the actual structure is defined * as a byte: used to calculate offset/shift/mask of each field */ #define BE_TGT_CTX_UPDT_CMD … struct amap_iscsi_target_context_update_wrb { … } __packed; #define BEISCSI_MAX_RECV_DATASEG_LEN … #define BEISCSI_MAX_CXNS … struct amap_iscsi_target_context_update_wrb_v2 { … } __packed; struct be_ring { … }; struct hwi_controller { … }; enum hwh_type_enum { … }; struct wrb_handle { … }; struct hwi_context_memory { … }; void beiscsi_start_boot_work(struct beiscsi_hba *phba, unsigned int s_handle); /* Logging related definitions */ #define BEISCSI_LOG_INIT … #define BEISCSI_LOG_MBOX … #define BEISCSI_LOG_MISC … #define BEISCSI_LOG_EH … #define BEISCSI_LOG_IO … #define BEISCSI_LOG_CONFIG … #define BEISCSI_LOG_ISCSI … #define __beiscsi_log(phba, level, fmt, arg...) … #define beiscsi_log(phba, level, mask, fmt, arg...) … #endif
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