// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2017 Hisilicon Limited. */ #include <linux/sched/clock.h> #include "hisi_sas.h" #define DRV_NAME … /* global registers need init */ #define DLVRY_QUEUE_ENABLE … #define IOST_BASE_ADDR_LO … #define IOST_BASE_ADDR_HI … #define ITCT_BASE_ADDR_LO … #define ITCT_BASE_ADDR_HI … #define IO_BROKEN_MSG_ADDR_LO … #define IO_BROKEN_MSG_ADDR_HI … #define PHY_CONTEXT … #define PHY_STATE … #define PHY_PORT_NUM_MA … #define PHY_CONN_RATE … #define ITCT_CLR … #define ITCT_CLR_EN_OFF … #define ITCT_CLR_EN_MSK … #define ITCT_DEV_OFF … #define ITCT_DEV_MSK … #define SAS_AXI_USER3 … #define IO_SATA_BROKEN_MSG_ADDR_LO … #define IO_SATA_BROKEN_MSG_ADDR_HI … #define SATA_INITI_D2H_STORE_ADDR_LO … #define SATA_INITI_D2H_STORE_ADDR_HI … #define CFG_MAX_TAG … #define TRANS_LOCK_ICT_TIME … #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL … #define HGC_SAS_TXFAIL_RETRY_CTRL … #define HGC_GET_ITV_TIME … #define DEVICE_MSG_WORK_MODE … #define OPENA_WT_CONTI_TIME … #define I_T_NEXUS_LOSS_TIME … #define MAX_CON_TIME_LIMIT_TIME … #define BUS_INACTIVE_LIMIT_TIME … #define REJECT_TO_OPEN_LIMIT_TIME … #define CQ_INT_CONVERGE_EN … #define CFG_AGING_TIME … #define HGC_DFX_CFG2 … #define CFG_ABT_SET_QUERY_IPTT … #define CFG_SET_ABORTED_IPTT_OFF … #define CFG_SET_ABORTED_IPTT_MSK … #define CFG_SET_ABORTED_EN_OFF … #define CFG_ABT_SET_IPTT_DONE … #define CFG_ABT_SET_IPTT_DONE_OFF … #define HGC_IOMB_PROC1_STATUS … #define HGC_LM_DFX_STATUS2 … #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF … #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK … #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF … #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK … #define HGC_CQE_ECC_ADDR … #define HGC_CQE_ECC_1B_ADDR_OFF … #define HGC_CQE_ECC_1B_ADDR_MSK … #define HGC_CQE_ECC_MB_ADDR_OFF … #define HGC_CQE_ECC_MB_ADDR_MSK … #define HGC_IOST_ECC_ADDR … #define HGC_IOST_ECC_1B_ADDR_OFF … #define HGC_IOST_ECC_1B_ADDR_MSK … #define HGC_IOST_ECC_MB_ADDR_OFF … #define HGC_IOST_ECC_MB_ADDR_MSK … #define HGC_DQE_ECC_ADDR … #define HGC_DQE_ECC_1B_ADDR_OFF … #define HGC_DQE_ECC_1B_ADDR_MSK … #define HGC_DQE_ECC_MB_ADDR_OFF … #define HGC_DQE_ECC_MB_ADDR_MSK … #define CHNL_INT_STATUS … #define TAB_DFX … #define HGC_ITCT_ECC_ADDR … #define HGC_ITCT_ECC_1B_ADDR_OFF … #define HGC_ITCT_ECC_1B_ADDR_MSK … #define HGC_ITCT_ECC_MB_ADDR_OFF … #define HGC_ITCT_ECC_MB_ADDR_MSK … #define HGC_AXI_FIFO_ERR_INFO … #define AXI_ERR_INFO_OFF … #define AXI_ERR_INFO_MSK … #define FIFO_ERR_INFO_OFF … #define FIFO_ERR_INFO_MSK … #define TAB_RD_TYPE … #define INT_COAL_EN … #define OQ_INT_COAL_TIME … #define OQ_INT_COAL_CNT … #define ENT_INT_COAL_TIME … #define ENT_INT_COAL_CNT … #define OQ_INT_SRC … #define OQ_INT_SRC_MSK … #define ENT_INT_SRC1 … #define ENT_INT_SRC1_D2H_FIS_CH0_OFF … #define ENT_INT_SRC1_D2H_FIS_CH0_MSK … #define ENT_INT_SRC1_D2H_FIS_CH1_OFF … #define ENT_INT_SRC1_D2H_FIS_CH1_MSK … #define ENT_INT_SRC2 … #define ENT_INT_SRC3 … #define ENT_INT_SRC3_WP_DEPTH_OFF … #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF … #define ENT_INT_SRC3_RP_DEPTH_OFF … #define ENT_INT_SRC3_AXI_OFF … #define ENT_INT_SRC3_FIFO_OFF … #define ENT_INT_SRC3_LM_OFF … #define ENT_INT_SRC3_ITC_INT_OFF … #define ENT_INT_SRC3_ITC_INT_MSK … #define ENT_INT_SRC3_ABT_OFF … #define ENT_INT_SRC3_DQE_POISON_OFF … #define ENT_INT_SRC3_IOST_POISON_OFF … #define ENT_INT_SRC3_ITCT_POISON_OFF … #define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF … #define ENT_INT_SRC_MSK1 … #define ENT_INT_SRC_MSK2 … #define ENT_INT_SRC_MSK3 … #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF … #define CHNL_PHYUPDOWN_INT_MSK … #define CHNL_ENT_INT_MSK … #define HGC_COM_INT_MSK … #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK … #define SAS_ECC_INTR … #define SAS_ECC_INTR_DQE_ECC_1B_OFF … #define SAS_ECC_INTR_DQE_ECC_MB_OFF … #define SAS_ECC_INTR_IOST_ECC_1B_OFF … #define SAS_ECC_INTR_IOST_ECC_MB_OFF … #define SAS_ECC_INTR_ITCT_ECC_1B_OFF … #define SAS_ECC_INTR_ITCT_ECC_MB_OFF … #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF … #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF … #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF … #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF … #define SAS_ECC_INTR_CQE_ECC_1B_OFF … #define SAS_ECC_INTR_CQE_ECC_MB_OFF … #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF … #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF … #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF … #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF … #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF … #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF … #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF … #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF … #define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF … #define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF … #define SAS_ECC_INTR_MSK … #define HGC_ERR_STAT_EN … #define CQE_SEND_CNT … #define DLVRY_Q_0_BASE_ADDR_LO … #define DLVRY_Q_0_BASE_ADDR_HI … #define DLVRY_Q_0_DEPTH … #define DLVRY_Q_0_WR_PTR … #define DLVRY_Q_0_RD_PTR … #define HYPER_STREAM_ID_EN_CFG … #define OQ0_INT_SRC_MSK … #define COMPL_Q_0_BASE_ADDR_LO … #define COMPL_Q_0_BASE_ADDR_HI … #define COMPL_Q_0_DEPTH … #define COMPL_Q_0_WR_PTR … #define COMPL_Q_0_RD_PTR … #define HGC_RXM_DFX_STATUS14 … #define HGC_RXM_DFX_STATUS14_MEM0_OFF … #define HGC_RXM_DFX_STATUS14_MEM0_MSK … #define HGC_RXM_DFX_STATUS14_MEM1_OFF … #define HGC_RXM_DFX_STATUS14_MEM1_MSK … #define HGC_RXM_DFX_STATUS14_MEM2_OFF … #define HGC_RXM_DFX_STATUS14_MEM2_MSK … #define HGC_RXM_DFX_STATUS15 … #define HGC_RXM_DFX_STATUS15_MEM3_OFF … #define HGC_RXM_DFX_STATUS15_MEM3_MSK … #define AWQOS_AWCACHE_CFG … #define ARQOS_ARCACHE_CFG … #define HILINK_ERR_DFX … #define SAS_GPIO_CFG_0 … #define SAS_GPIO_CFG_1 … #define SAS_GPIO_TX_0_1 … #define SAS_CFG_DRIVE_VLD … /* phy registers requiring init */ #define PORT_BASE … #define PHY_CFG … #define HARD_PHY_LINKRATE … #define PHY_CFG_ENA_OFF … #define PHY_CFG_ENA_MSK … #define PHY_CFG_DC_OPT_OFF … #define PHY_CFG_DC_OPT_MSK … #define PHY_CFG_PHY_RST_OFF … #define PHY_CFG_PHY_RST_MSK … #define PROG_PHY_LINK_RATE … #define CFG_PROG_PHY_LINK_RATE_OFF … #define CFG_PROG_PHY_LINK_RATE_MSK … #define CFG_PROG_OOB_PHY_LINK_RATE_OFF … #define CFG_PROG_OOB_PHY_LINK_RATE_MSK … #define PHY_CTRL … #define PHY_CTRL_RESET_OFF … #define PHY_CTRL_RESET_MSK … #define CMD_HDR_PIR_OFF … #define CMD_HDR_PIR_MSK … #define SERDES_CFG … #define CFG_ALOS_CHK_DISABLE_OFF … #define CFG_ALOS_CHK_DISABLE_MSK … #define SAS_PHY_BIST_CTRL … #define CFG_BIST_MODE_SEL_OFF … #define CFG_BIST_MODE_SEL_MSK … #define CFG_LOOP_TEST_MODE_OFF … #define CFG_LOOP_TEST_MODE_MSK … #define CFG_RX_BIST_EN_OFF … #define CFG_RX_BIST_EN_MSK … #define CFG_TX_BIST_EN_OFF … #define CFG_TX_BIST_EN_MSK … #define CFG_BIST_TEST_OFF … #define CFG_BIST_TEST_MSK … #define SAS_PHY_BIST_CODE … #define SAS_PHY_BIST_CODE1 … #define SAS_BIST_ERR_CNT … #define SL_CFG … #define AIP_LIMIT … #define SL_CONTROL … #define SL_CONTROL_NOTIFY_EN_OFF … #define SL_CONTROL_NOTIFY_EN_MSK … #define SL_CTA_OFF … #define SL_CTA_MSK … #define RX_PRIMS_STATUS … #define RX_BCAST_CHG_OFF … #define RX_BCAST_CHG_MSK … #define TX_ID_DWORD0 … #define TX_ID_DWORD1 … #define TX_ID_DWORD2 … #define TX_ID_DWORD3 … #define TX_ID_DWORD4 … #define TX_ID_DWORD5 … #define TX_ID_DWORD6 … #define TXID_AUTO … #define CT3_OFF … #define CT3_MSK … #define TX_HARDRST_OFF … #define TX_HARDRST_MSK … #define RX_IDAF_DWORD0 … #define RXOP_CHECK_CFG_H … #define STP_LINK_TIMER … #define STP_LINK_TIMEOUT_STATE … #define CON_CFG_DRIVER … #define SAS_SSP_CON_TIMER_CFG … #define SAS_SMP_CON_TIMER_CFG … #define SAS_STP_CON_TIMER_CFG … #define CHL_INT0 … #define CHL_INT0_HOTPLUG_TOUT_OFF … #define CHL_INT0_HOTPLUG_TOUT_MSK … #define CHL_INT0_SL_RX_BCST_ACK_OFF … #define CHL_INT0_SL_RX_BCST_ACK_MSK … #define CHL_INT0_SL_PHY_ENABLE_OFF … #define CHL_INT0_SL_PHY_ENABLE_MSK … #define CHL_INT0_NOT_RDY_OFF … #define CHL_INT0_NOT_RDY_MSK … #define CHL_INT0_PHY_RDY_OFF … #define CHL_INT0_PHY_RDY_MSK … #define CHL_INT1 … #define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF … #define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF … #define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF … #define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF … #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF … #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF … #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF … #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF … #define CHL_INT1_DMAC_TX_FIFO_ERR_OFF … #define CHL_INT1_DMAC_RX_FIFO_ERR_OFF … #define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF … #define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF … #define CHL_INT2 … #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF … #define CHL_INT2_RX_DISP_ERR_OFF … #define CHL_INT2_RX_CODE_ERR_OFF … #define CHL_INT2_RX_INVLD_DW_OFF … #define CHL_INT2_STP_LINK_TIMEOUT_OFF … #define CHL_INT0_MSK … #define CHL_INT1_MSK … #define CHL_INT2_MSK … #define SAS_EC_INT_COAL_TIME … #define CHL_INT_COAL_EN … #define SAS_RX_TRAIN_TIMER … #define PHY_CTRL_RDY_MSK … #define PHYCTRL_NOT_RDY_MSK … #define PHYCTRL_DWS_RESET_MSK … #define PHYCTRL_PHY_ENA_MSK … #define SL_RX_BCAST_CHK_MSK … #define PHYCTRL_OOB_RESTART_MSK … #define DMA_TX_STATUS … #define DMA_TX_STATUS_BUSY_OFF … #define DMA_TX_STATUS_BUSY_MSK … #define DMA_RX_STATUS … #define DMA_RX_STATUS_BUSY_OFF … #define DMA_RX_STATUS_BUSY_MSK … #define COARSETUNE_TIME … #define TXDEEMPH_G1 … #define ERR_CNT_DWS_LOST … #define ERR_CNT_RESET_PROB … #define ERR_CNT_INVLD_DW … #define ERR_CNT_CODE_ERR … #define ERR_CNT_DISP_ERR … #define DFX_FIFO_CTRL … #define DFX_FIFO_CTRL_TRIGGER_MODE_OFF … #define DFX_FIFO_CTRL_TRIGGER_MODE_MSK … #define DFX_FIFO_CTRL_DUMP_MODE_OFF … #define DFX_FIFO_CTRL_DUMP_MODE_MSK … #define DFX_FIFO_CTRL_SIGNAL_SEL_OFF … #define DFX_FIFO_CTRL_SIGNAL_SEL_MSK … #define DFX_FIFO_CTRL_DUMP_DISABLE_OFF … #define DFX_FIFO_CTRL_DUMP_DISABLE_MSK … #define DFX_FIFO_TRIGGER … #define DFX_FIFO_TRIGGER_MSK … #define DFX_FIFO_DUMP_MSK … #define DFX_FIFO_RD_DATA … #define DEFAULT_ITCT_HW … #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) #error Max ITCT exceeded #endif #define AXI_MASTER_CFG_BASE … #define AM_CTRL_GLOBAL … #define AM_CTRL_SHUTDOWN_REQ_OFF … #define AM_CTRL_SHUTDOWN_REQ_MSK … #define AM_CURR_TRANS_RETURN … #define AM_CFG_MAX_TRANS … #define AM_CFG_SINGLE_PORT_MAX_TRANS … #define AXI_CFG … #define AM_ROB_ECC_ERR_ADDR … #define AM_ROB_ECC_ERR_ADDR_OFF … #define AM_ROB_ECC_ERR_ADDR_MSK … /* RAS registers need init */ #define RAS_BASE … #define SAS_RAS_INTR0 … #define SAS_RAS_INTR1 … #define SAS_RAS_INTR0_MASK … #define SAS_RAS_INTR1_MASK … #define CFG_SAS_RAS_INTR_MASK … #define SAS_RAS_INTR2 … #define SAS_RAS_INTR2_MASK … /* HW dma structures */ /* Delivery queue header */ /* dw0 */ #define CMD_HDR_ABORT_FLAG_OFF … #define CMD_HDR_ABORT_FLAG_MSK … #define CMD_HDR_ABORT_DEVICE_TYPE_OFF … #define CMD_HDR_ABORT_DEVICE_TYPE_MSK … #define CMD_HDR_RESP_REPORT_OFF … #define CMD_HDR_RESP_REPORT_MSK … #define CMD_HDR_TLR_CTRL_OFF … #define CMD_HDR_TLR_CTRL_MSK … #define CMD_HDR_PORT_OFF … #define CMD_HDR_PORT_MSK … #define CMD_HDR_PRIORITY_OFF … #define CMD_HDR_PRIORITY_MSK … #define CMD_HDR_CMD_OFF … #define CMD_HDR_CMD_MSK … /* dw1 */ #define CMD_HDR_UNCON_CMD_OFF … #define CMD_HDR_DIR_OFF … #define CMD_HDR_DIR_MSK … #define CMD_HDR_RESET_OFF … #define CMD_HDR_RESET_MSK … #define CMD_HDR_VDTL_OFF … #define CMD_HDR_VDTL_MSK … #define CMD_HDR_FRAME_TYPE_OFF … #define CMD_HDR_FRAME_TYPE_MSK … #define CMD_HDR_DEV_ID_OFF … #define CMD_HDR_DEV_ID_MSK … /* dw2 */ #define CMD_HDR_CFL_OFF … #define CMD_HDR_CFL_MSK … #define CMD_HDR_NCQ_TAG_OFF … #define CMD_HDR_NCQ_TAG_MSK … #define CMD_HDR_MRFL_OFF … #define CMD_HDR_MRFL_MSK … #define CMD_HDR_SG_MOD_OFF … #define CMD_HDR_SG_MOD_MSK … /* dw3 */ #define CMD_HDR_IPTT_OFF … #define CMD_HDR_IPTT_MSK … /* dw6 */ #define CMD_HDR_DIF_SGL_LEN_OFF … #define CMD_HDR_DIF_SGL_LEN_MSK … #define CMD_HDR_DATA_SGL_LEN_OFF … #define CMD_HDR_DATA_SGL_LEN_MSK … /* dw7 */ #define CMD_HDR_ADDR_MODE_SEL_OFF … #define CMD_HDR_ADDR_MODE_SEL_MSK … #define CMD_HDR_ABORT_IPTT_OFF … #define CMD_HDR_ABORT_IPTT_MSK … /* Completion header */ /* dw0 */ #define CMPLT_HDR_CMPLT_OFF … #define CMPLT_HDR_CMPLT_MSK … #define CMPLT_HDR_ERROR_PHASE_OFF … #define CMPLT_HDR_ERROR_PHASE_MSK … /* bit[9:2] Error Phase */ #define ERR_PHASE_RESPONSE_FRAME_REV_STAGE_OFF … #define ERR_PHASE_RESPONSE_FRAME_REV_STAGE_MSK … #define CMPLT_HDR_RSPNS_XFRD_OFF … #define CMPLT_HDR_RSPNS_XFRD_MSK … #define CMPLT_HDR_RSPNS_GOOD_OFF … #define CMPLT_HDR_RSPNS_GOOD_MSK … #define CMPLT_HDR_ERX_OFF … #define CMPLT_HDR_ERX_MSK … #define CMPLT_HDR_ABORT_STAT_OFF … #define CMPLT_HDR_ABORT_STAT_MSK … /* abort_stat */ #define STAT_IO_NOT_VALID … #define STAT_IO_NO_DEVICE … #define STAT_IO_COMPLETE … #define STAT_IO_ABORTED … /* dw1 */ #define CMPLT_HDR_IPTT_OFF … #define CMPLT_HDR_IPTT_MSK … #define CMPLT_HDR_DEV_ID_OFF … #define CMPLT_HDR_DEV_ID_MSK … /* dw3 */ #define SATA_DISK_IN_ERROR_STATUS_OFF … #define SATA_DISK_IN_ERROR_STATUS_MSK … #define CMPLT_HDR_SATA_DISK_ERR_OFF … #define CMPLT_HDR_SATA_DISK_ERR_MSK … #define CMPLT_HDR_IO_IN_TARGET_OFF … #define CMPLT_HDR_IO_IN_TARGET_MSK … /* bit[23:18] ERR_FIS_ATA_STATUS */ #define FIS_ATA_STATUS_ERR_OFF … #define FIS_ATA_STATUS_ERR_MSK … #define FIS_TYPE_SDB_OFF … #define FIS_TYPE_SDB_MSK … /* ITCT header */ /* qw0 */ #define ITCT_HDR_DEV_TYPE_OFF … #define ITCT_HDR_DEV_TYPE_MSK … #define ITCT_HDR_VALID_OFF … #define ITCT_HDR_VALID_MSK … #define ITCT_HDR_MCR_OFF … #define ITCT_HDR_MCR_MSK … #define ITCT_HDR_VLN_OFF … #define ITCT_HDR_VLN_MSK … #define ITCT_HDR_SMP_TIMEOUT_OFF … #define ITCT_HDR_AWT_CONTINUE_OFF … #define ITCT_HDR_PORT_ID_OFF … #define ITCT_HDR_PORT_ID_MSK … /* qw2 */ #define ITCT_HDR_INLT_OFF … #define ITCT_HDR_INLT_MSK … #define ITCT_HDR_RTOLT_OFF … #define ITCT_HDR_RTOLT_MSK … struct hisi_sas_protect_iu_v3_hw { … }; struct hisi_sas_complete_v3_hdr { … }; struct hisi_sas_err_record_v3 { … }; #define RX_DATA_LEN_UNDERFLOW_OFF … #define RX_DATA_LEN_UNDERFLOW_MSK … #define RX_FIS_STATUS_ERR_OFF … #define RX_FIS_STATUS_ERR_MSK … #define HISI_SAS_COMMAND_ENTRIES_V3_HW … #define HISI_SAS_MSI_COUNT_V3_HW … #define DIR_NO_DATA … #define DIR_TO_INI … #define DIR_TO_DEVICE … #define DIR_RESERVED … #define FIS_CMD_IS_UNCONSTRAINED(fis) … #define T10_INSRT_EN_OFF … #define T10_INSRT_EN_MSK … #define T10_RMV_EN_OFF … #define T10_RMV_EN_MSK … #define T10_RPLC_EN_OFF … #define T10_RPLC_EN_MSK … #define T10_CHK_EN_OFF … #define T10_CHK_EN_MSK … #define INCR_LBRT_OFF … #define INCR_LBRT_MSK … #define USR_DATA_BLOCK_SZ_OFF … #define USR_DATA_BLOCK_SZ_MSK … #define T10_CHK_MSK_OFF … #define T10_CHK_REF_TAG_MSK … #define T10_CHK_APP_TAG_MSK … #define BASE_VECTORS_V3_HW … #define MIN_AFFINE_VECTORS_V3_HW … #define CHNL_INT_STS_MSK … #define CHNL_INT_STS_PHY_MSK … #define CHNL_INT_STS_INT0_MSK … #define CHNL_INT_STS_INT1_MSK … #define CHNL_INT_STS_INT2_MSK … #define CHNL_WIDTH … #define BAR_NO_V3_HW … enum { … }; static bool hisi_sas_intr_conv; MODULE_PARM_DESC(…) …; /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */ static int prot_mask; module_param(prot_mask, int, 0444); MODULE_PARM_DESC(…) …; /* the index of iopoll queues are bigger than interrupt queues' */ static int experimental_iopoll_q_cnt; module_param(experimental_iopoll_q_cnt, int, 0444); MODULE_PARM_DESC(…) …; static int debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba); static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) { … } static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) { … } static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, u32 off, u32 val) { … } static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, int phy_no, u32 off) { … } #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ timeout_us) … #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ timeout_us) … static void interrupt_enable_v3_hw(struct hisi_hba *hisi_hba) { … } static void init_reg_v3_hw(struct hisi_hba *hisi_hba) { … } static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_device *sas_dev) { … } static int clear_itct_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_device *sas_dev) { … } static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, struct domain_device *device) { … } static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) { … } static int hw_init_v3_hw(struct hisi_hba *hisi_hba) { … } static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) { … } static void phys_init_v3_hw(struct hisi_hba *hisi_hba) { … } static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) { … } static void start_delivery_v3_hw(struct hisi_sas_dq *dq) { … } static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot, struct hisi_sas_cmd_hdr *hdr, struct scatterlist *scatter, int n_elem) { … } static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot, struct hisi_sas_cmd_hdr *hdr, struct scatterlist *scatter, int n_elem) { … } static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd) { … } static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd, struct hisi_sas_protect_iu_v3_hw *prot) { … } static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { … } static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { … } static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { … } static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { … } static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) { … } static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) { … } static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) { … } static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) { … } static const struct hisi_sas_hw_error port_axi_error[] = …; static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) { … } static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = …; static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba, u32 irq_value) { … } static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba) { … } static const struct hisi_sas_hw_error axi_error[] = …; static const struct hisi_sas_hw_error fifo_error[] = …; static const struct hisi_sas_hw_error fatal_axi_error[] = …; static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) { … } static bool is_ncq_err_v3_hw(struct hisi_sas_complete_v3_hdr *complete_hdr) { … } static bool slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, struct hisi_sas_slot *slot) { … } static void slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { … } static int complete_v3_hw(struct hisi_sas_cq *cq) { … } static int queue_complete_v3_hw(struct Scsi_Host *shost, unsigned int queue) { … } static irqreturn_t cq_thread_v3_hw(int irq_no, void *p) { … } static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) { … } static void hisi_sas_v3_free_vectors(void *data) { … } static int interrupt_preinit_v3_hw(struct hisi_hba *hisi_hba) { … } static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) { … } static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) { … } static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, struct sas_phy_linkrates *r) { … } static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) { … } static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) { … } static int disable_host_v3_hw(struct hisi_hba *hisi_hba) { … } static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) { … } static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, u8 reg_index, u8 reg_count, u8 *write_data) { … } static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, int delay_ms, int timeout_ms) { … } static ssize_t intr_conv_v3_hw_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static DEVICE_ATTR_RO(intr_conv_v3_hw); static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba) { … } static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw); static ssize_t intr_coal_count_v3_hw_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t intr_coal_count_v3_hw_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static DEVICE_ATTR_RW(intr_coal_count_v3_hw); static ssize_t iopoll_q_cnt_v3_hw_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static DEVICE_ATTR_RO(iopoll_q_cnt_v3_hw); static int device_configure_v3_hw(struct scsi_device *sdev, struct queue_limits *lim) { … } static struct attribute *host_v3_hw_attrs[] = …; ATTRIBUTE_GROUPS(…); static const struct attribute_group *sdev_groups_v3_hw[] = …; #define HISI_SAS_DEBUGFS_REG(x) … struct hisi_sas_debugfs_reg_lu { … }; struct hisi_sas_debugfs_reg { … }; static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = …; static const struct hisi_sas_debugfs_reg debugfs_port_reg = …; static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = …; static const struct hisi_sas_debugfs_reg debugfs_global_reg = …; static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = …; static const struct hisi_sas_debugfs_reg debugfs_axi_reg = …; static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = …; static const struct hisi_sas_debugfs_reg debugfs_ras_reg = …; static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba) { … } static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba) { … } static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba, enum hisi_sas_debugfs_cache_type type, u32 *cache) { … } static void hisi_sas_bist_test_prep_v3_hw(struct hisi_hba *hisi_hba) { … } static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba) { … } #define SAS_PHY_BIST_CODE_INIT … #define SAS_PHY_BIST_CODE1_INIT … static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable) { … } static void hisi_sas_map_queues(struct Scsi_Host *shost) { … } static const struct scsi_host_template sht_v3_hw = …; static const struct hisi_sas_hw hisi_sas_v3_hw = …; static struct Scsi_Host * hisi_sas_shost_alloc_pci(struct pci_dev *pdev) { … } static void debugfs_snapshot_cq_reg_v3_hw(struct hisi_hba *hisi_hba) { … } static void debugfs_snapshot_dq_reg_v3_hw(struct hisi_hba *hisi_hba) { … } static void debugfs_snapshot_port_reg_v3_hw(struct hisi_hba *hisi_hba) { … } static void debugfs_snapshot_global_reg_v3_hw(struct hisi_hba *hisi_hba) { … } static void debugfs_snapshot_axi_reg_v3_hw(struct hisi_hba *hisi_hba) { … } static void debugfs_snapshot_ras_reg_v3_hw(struct hisi_hba *hisi_hba) { … } static void debugfs_snapshot_itct_reg_v3_hw(struct hisi_hba *hisi_hba) { … } static void debugfs_snapshot_iost_reg_v3_hw(struct hisi_hba *hisi_hba) { … } static const char * debugfs_to_reg_name_v3_hw(int off, int base_off, const struct hisi_sas_debugfs_reg_lu *lu) { … } static void debugfs_print_reg_v3_hw(u32 *regs_val, struct seq_file *s, const struct hisi_sas_debugfs_reg *reg) { … } static int debugfs_global_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_ATTRIBUTE(…); static int debugfs_axi_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_ATTRIBUTE(…); static int debugfs_ras_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_ATTRIBUTE(…); static int debugfs_port_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_ATTRIBUTE(…); static void debugfs_show_row_64_v3_hw(struct seq_file *s, int index, int sz, __le64 *ptr) { … } static void debugfs_show_row_32_v3_hw(struct seq_file *s, int index, int sz, __le32 *ptr) { … } static void debugfs_cq_show_slot_v3_hw(struct seq_file *s, int slot, struct hisi_sas_debugfs_cq *debugfs_cq) { … } static int debugfs_cq_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_ATTRIBUTE(…); static void debugfs_dq_show_slot_v3_hw(struct seq_file *s, int slot, void *dq_ptr) { … } static int debugfs_dq_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_ATTRIBUTE(…); static int debugfs_iost_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_ATTRIBUTE(…); static int debugfs_iost_cache_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_ATTRIBUTE(…); static int debugfs_itct_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_ATTRIBUTE(…); static int debugfs_itct_cache_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_ATTRIBUTE(…); static void debugfs_create_files_v3_hw(struct hisi_hba *hisi_hba) { … } static ssize_t debugfs_trigger_dump_v3_hw_write(struct file *file, const char __user *user_buf, size_t count, loff_t *ppos) { … } static const struct file_operations debugfs_trigger_dump_v3_hw_fops = …; enum { … }; static const struct { … } debugfs_loop_linkrate_v3_hw[] = …; static int debugfs_bist_linkrate_v3_hw_show(struct seq_file *s, void *p) { … } static ssize_t debugfs_bist_linkrate_v3_hw_write(struct file *filp, const char __user *buf, size_t count, loff_t *ppos) { … } DEFINE_SHOW_STORE_ATTRIBUTE(…); static const struct { … } debugfs_loop_code_mode_v3_hw[] = …; static int debugfs_bist_code_mode_v3_hw_show(struct seq_file *s, void *p) { … } static ssize_t debugfs_bist_code_mode_v3_hw_write(struct file *filp, const char __user *buf, size_t count, loff_t *ppos) { … } DEFINE_SHOW_STORE_ATTRIBUTE(…); static ssize_t debugfs_bist_phy_v3_hw_write(struct file *filp, const char __user *buf, size_t count, loff_t *ppos) { … } static int debugfs_bist_phy_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_STORE_ATTRIBUTE(…); static ssize_t debugfs_bist_cnt_v3_hw_write(struct file *filp, const char __user *buf, size_t count, loff_t *ppos) { … } static int debugfs_bist_cnt_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_STORE_ATTRIBUTE(…); static const struct { … } debugfs_loop_modes_v3_hw[] = …; static int debugfs_bist_mode_v3_hw_show(struct seq_file *s, void *p) { … } static ssize_t debugfs_bist_mode_v3_hw_write(struct file *filp, const char __user *buf, size_t count, loff_t *ppos) { … } DEFINE_SHOW_STORE_ATTRIBUTE(…); static ssize_t debugfs_bist_enable_v3_hw_write(struct file *filp, const char __user *buf, size_t count, loff_t *ppos) { … } static int debugfs_bist_enable_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_STORE_ATTRIBUTE(…); static const struct { … } debugfs_ffe_name_v3_hw[FFE_CFG_MAX] = …; static ssize_t debugfs_v3_hw_write(struct file *filp, const char __user *buf, size_t count, loff_t *ppos) { … } static int debugfs_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_STORE_ATTRIBUTE(…); static ssize_t debugfs_phy_down_cnt_v3_hw_write(struct file *filp, const char __user *buf, size_t count, loff_t *ppos) { … } static int debugfs_phy_down_cnt_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_STORE_ATTRIBUTE(…); enum fifo_dump_mode_v3_hw { … }; enum fifo_trigger_mode_v3_hw { … }; static int debugfs_is_fifo_config_valid_v3_hw(struct hisi_sas_phy *phy) { … } static int debugfs_update_fifo_config_v3_hw(struct hisi_sas_phy *phy) { … } static ssize_t debugfs_fifo_update_cfg_v3_hw_write(struct file *filp, const char __user *buf, size_t count, loff_t *ppos) { … } static const struct file_operations debugfs_fifo_update_cfg_v3_hw_fops = …; static void debugfs_read_fifo_data_v3_hw(struct hisi_sas_phy *phy) { … } static int debugfs_fifo_data_v3_hw_show(struct seq_file *s, void *p) { … } DEFINE_SHOW_ATTRIBUTE(…); static void debugfs_fifo_init_v3_hw(struct hisi_hba *hisi_hba) { … } static void debugfs_release_v3_hw(struct hisi_hba *hisi_hba, int dump_index) { … } static const struct hisi_sas_debugfs_reg *debugfs_reg_array_v3_hw[DEBUGFS_REGS_NUM] = …; static int debugfs_alloc_v3_hw(struct hisi_hba *hisi_hba, int dump_index) { … } static int debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba) { … } static void debugfs_phy_down_cnt_init_v3_hw(struct hisi_hba *hisi_hba) { … } static void debugfs_bist_init_v3_hw(struct hisi_hba *hisi_hba) { … } static void debugfs_exit_v3_hw(struct hisi_hba *hisi_hba) { … } static void debugfs_init_v3_hw(struct hisi_hba *hisi_hba) { … } static int hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) { … } static void hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) { … } static void hisi_sas_v3_remove(struct pci_dev *pdev) { … } static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) { … } static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) { … } enum { … }; static void enable_host_v3_hw(struct hisi_hba *hisi_hba) { … } static int _suspend_v3_hw(struct device *device) { … } static int _resume_v3_hw(struct device *device) { … } static int __maybe_unused suspend_v3_hw(struct device *device) { … } static int __maybe_unused resume_v3_hw(struct device *device) { … } static const struct pci_device_id sas_v3_pci_table[] = …; MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); static const struct pci_error_handlers hisi_sas_err_handler = …; static UNIVERSAL_DEV_PM_OPS(hisi_sas_v3_pm_ops, suspend_v3_hw, resume_v3_hw, NULL); static struct pci_driver sas_v3_pci_driver = …; module_pci_driver(…) …; module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444); MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_ALIAS(…) …;
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