/* SPDX-License-Identifier: GPL-2.0 */ /* * NCR 5380 defines * * Copyright 1993, Drew Eckhardt * Visionary Computing * (Unix consulting and custom programming) * [email protected] * +1 (303) 666-5836 * * For more information, please consult * * NCR 5380 Family * SCSI Protocol Controller * Databook * NCR Microelectronics * 1635 Aeroplaza Drive * Colorado Springs, CO 80916 * 1+ (719) 578-3400 * 1+ (800) 334-5454 */ #ifndef NCR5380_H #define NCR5380_H #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/list.h> #include <linux/workqueue.h> #include <scsi/scsi_dbg.h> #include <scsi/scsi_eh.h> #include <scsi/scsi_transport_spi.h> #define NDEBUG_ARBITRATION … #define NDEBUG_AUTOSENSE … #define NDEBUG_DMA … #define NDEBUG_HANDSHAKE … #define NDEBUG_INFORMATION … #define NDEBUG_INIT … #define NDEBUG_INTR … #define NDEBUG_LINKED … #define NDEBUG_MAIN … #define NDEBUG_NO_DATAOUT … #define NDEBUG_NO_WRITE … #define NDEBUG_PIO … #define NDEBUG_PSEUDO_DMA … #define NDEBUG_QUEUES … #define NDEBUG_RESELECTION … #define NDEBUG_SELECTION … #define NDEBUG_USLEEP … #define NDEBUG_LAST_BYTE_SENT … #define NDEBUG_RESTART_SELECT … #define NDEBUG_EXTENDED … #define NDEBUG_C400_PREAD … #define NDEBUG_C400_PWRITE … #define NDEBUG_LISTS … #define NDEBUG_ABORT … #define NDEBUG_TAGS … #define NDEBUG_MERGING … #define NDEBUG_ANY … /* * The contents of the OUTPUT DATA register are asserted on the bus when * either arbitration is occurring or the phase-indicating signals ( * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA * bit in the INITIATOR COMMAND register is set. */ #define OUTPUT_DATA_REG … #define CURRENT_SCSI_DATA_REG … #define INITIATOR_COMMAND_REG … #define ICR_ASSERT_RST … #define ICR_ARBITRATION_PROGRESS … #define ICR_TRI_STATE … #define ICR_ARBITRATION_LOST … #define ICR_DIFF_ENABLE … #define ICR_ASSERT_ACK … #define ICR_ASSERT_BSY … #define ICR_ASSERT_SEL … #define ICR_ASSERT_ATN … #define ICR_ASSERT_DATA … #define ICR_BASE … #define MODE_REG … /* * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the * transfer, causing the chip to hog the bus. You probably don't want * this. */ #define MR_BLOCK_DMA_MODE … #define MR_TARGET … #define MR_ENABLE_PAR_CHECK … #define MR_ENABLE_PAR_INTR … #define MR_ENABLE_EOP_INTR … #define MR_MONITOR_BSY … #define MR_DMA_MODE … #define MR_ARBITRATE … #define MR_BASE … #define TARGET_COMMAND_REG … #define TCR_LAST_BYTE_SENT … #define TCR_ASSERT_REQ … #define TCR_ASSERT_MSG … #define TCR_ASSERT_CD … #define TCR_ASSERT_IO … #define STATUS_REG … /* * Note : a set bit indicates an active signal, driven by us or another * device. */ #define SR_RST … #define SR_BSY … #define SR_REQ … #define SR_MSG … #define SR_CD … #define SR_IO … #define SR_SEL … #define SR_DBP … /* * Setting a bit in this register will cause an interrupt to be generated when * BSY is false and SEL true and this bit is asserted on the bus. */ #define SELECT_ENABLE_REG … #define BUS_AND_STATUS_REG … #define BASR_END_DMA_TRANSFER … #define BASR_DRQ … #define BASR_PARITY_ERROR … #define BASR_IRQ … #define BASR_PHASE_MATCH … #define BASR_BUSY_ERROR … #define BASR_ATN … #define BASR_ACK … /* Write any value to this register to start a DMA send */ #define START_DMA_SEND_REG … /* * Used in DMA transfer mode, data is latched from the SCSI bus on * the falling edge of REQ (ini) or ACK (tgt) */ #define INPUT_DATA_REG … /* Write any value to this register to start a DMA receive */ #define START_DMA_TARGET_RECEIVE_REG … /* Read this register to clear interrupt conditions */ #define RESET_PARITY_INTERRUPT_REG … /* Write any value to this register to start an ini mode DMA receive */ #define START_DMA_INITIATOR_RECEIVE_REG … /* NCR 53C400(A) Control Status Register bits: */ #define CSR_RESET … #define CSR_53C80_REG … #define CSR_TRANS_DIR … #define CSR_SCSI_BUFF_INTR … #define CSR_53C80_INTR … #define CSR_SHARED_INTR … #define CSR_HOST_BUF_NOT_RDY … #define CSR_SCSI_BUF_RDY … #define CSR_GATED_53C80_IRQ … #define CSR_BASE … /* Note : PHASE_* macros are based on the values of the STATUS register */ #define PHASE_MASK … #define PHASE_DATAOUT … #define PHASE_DATAIN … #define PHASE_CMDOUT … #define PHASE_STATIN … #define PHASE_MSGOUT … #define PHASE_MSGIN … #define PHASE_UNKNOWN … /* * Convert status register phase to something we can use to set phase in * the target register so we can get phase mismatch interrupts on DMA * transfers. */ #define PHASE_SR_TO_TCR(phase) … #ifndef NO_IRQ #define NO_IRQ … #endif #define FLAG_DMA_FIXUP … #define FLAG_NO_PSEUDO_DMA … #define FLAG_LATE_DMA_SETUP … #define FLAG_TOSHIBA_DELAY … struct NCR5380_hostdata { … }; struct NCR5380_cmd { … }; #define NCR5380_PIO_CHUNK_SIZE … /* Time limit (ms) to poll registers when IRQs are disabled, e.g. during PDMA */ #define NCR5380_REG_POLL_TIME … static inline struct scsi_cmnd *NCR5380_to_scmd(struct NCR5380_cmd *ncmd_ptr) { … } static inline struct NCR5380_cmd *NCR5380_to_ncmd(struct scsi_cmnd *cmd) { … } #ifndef NDEBUG #define NDEBUG … #endif #define dprintk(flg, fmt, ...) … #define dsprintk(flg, host, fmt, ...) … #if NDEBUG #define NCR5380_dprint … #define NCR5380_dprint_phase … static void NCR5380_print_phase(struct Scsi_Host *instance); static void NCR5380_print(struct Scsi_Host *instance); #else #define NCR5380_dprint(flg, arg) … #define NCR5380_dprint_phase(flg, arg) … #endif static int NCR5380_init(struct Scsi_Host *instance, int flags); static int NCR5380_maybe_reset_bus(struct Scsi_Host *); static void NCR5380_exit(struct Scsi_Host *instance); static void NCR5380_information_transfer(struct Scsi_Host *instance); static irqreturn_t NCR5380_intr(int irq, void *dev_id); static void NCR5380_main(struct work_struct *work); static const char *NCR5380_info(struct Scsi_Host *instance); static void NCR5380_reselect(struct Scsi_Host *instance); static bool NCR5380_select(struct Scsi_Host *, struct scsi_cmnd *); static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data); static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data, unsigned int can_sleep); static int NCR5380_poll_politely2(struct NCR5380_hostdata *, unsigned int, u8, u8, unsigned int, u8, u8, unsigned long); static inline int NCR5380_poll_politely(struct NCR5380_hostdata *hostdata, unsigned int reg, u8 bit, u8 val, unsigned long wait) { … } static int NCR5380_dma_xfer_len(struct NCR5380_hostdata *, struct scsi_cmnd *); static int NCR5380_dma_send_setup(struct NCR5380_hostdata *, unsigned char *, int); static int NCR5380_dma_recv_setup(struct NCR5380_hostdata *, unsigned char *, int); static int NCR5380_dma_residual(struct NCR5380_hostdata *); static inline int NCR5380_dma_xfer_none(struct NCR5380_hostdata *hostdata, struct scsi_cmnd *cmd) { … } static inline int NCR5380_dma_setup_none(struct NCR5380_hostdata *hostdata, unsigned char *data, int count) { … } static inline int NCR5380_dma_residual_none(struct NCR5380_hostdata *hostdata) { … } #endif /* NCR5380_H */
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