/* * Disk Array driver for HP Smart Array SAS controllers * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries * Copyright 2016 Microsemi Corporation * Copyright 2014-2015 PMC-Sierra, Inc. * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or * NON INFRINGEMENT. See the GNU General Public License for more details. * * Questions/Comments/Bugfixes to [email protected] * */ #ifndef HPSA_H #define HPSA_H #include <scsi/scsicam.h> #define IO_OK … #define IO_ERROR … struct ctlr_info; struct access_method { … }; /* for SAS hosts and SAS expanders */ struct hpsa_sas_node { … }; struct hpsa_sas_port { … }; struct hpsa_sas_phy { … }; #define EXTERNAL_QD … struct hpsa_scsi_dev_t { … }; struct reply_queue_buffer { … }; #pragma pack(1) struct bmic_controller_parameters { … }; #pragma pack() struct ctlr_info { … }; struct offline_device_entry { … }; #define HPSA_ABORT_MSG … #define HPSA_DEVICE_RESET_MSG … #define HPSA_RESET_TYPE_CONTROLLER … #define HPSA_RESET_TYPE_BUS … #define HPSA_RESET_TYPE_LUN … #define HPSA_PHYS_TARGET_RESET … #define HPSA_MSG_SEND_RETRY_LIMIT … #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS … /* Maximum time in seconds driver will wait for command completions * when polling before giving up. */ #define HPSA_MAX_POLL_TIME_SECS … /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines * how many times to retry TEST UNIT READY on a device * while waiting for it to become ready before giving up. * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval * between sending TURs while waiting for a device * to become ready. */ #define HPSA_TUR_RETRY_LIMIT … #define HPSA_MAX_WAIT_INTERVAL_SECS … /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board * to become ready, in seconds, before giving up on it. * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait * between polling the board to see if it is ready, in * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and * HPSA_BOARD_READY_ITERATIONS are derived from those. */ #define HPSA_BOARD_READY_WAIT_SECS … #define HPSA_BOARD_NOT_READY_WAIT_SECS … #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS … #define HPSA_BOARD_READY_POLL_INTERVAL … #define HPSA_BOARD_READY_ITERATIONS … #define HPSA_BOARD_NOT_READY_ITERATIONS … #define HPSA_POST_RESET_PAUSE_MSECS … #define HPSA_POST_RESET_NOOP_RETRIES … /* Defining the diffent access_menthods */ /* * Memory mapped FIFO interface (SMART 53xx cards) */ #define SA5_DOORBELL … #define SA5_REQUEST_PORT_OFFSET … #define SA5_REQUEST_PORT64_LO_OFFSET … #define SA5_REQUEST_PORT64_HI_OFFSET … #define SA5_REPLY_INTR_MASK_OFFSET … #define SA5_REPLY_PORT_OFFSET … #define SA5_INTR_STATUS … #define SA5_SCRATCHPAD_OFFSET … #define SA5_CTCFG_OFFSET … #define SA5_CTMEM_OFFSET … #define SA5_INTR_OFF … #define SA5B_INTR_OFF … #define SA5_INTR_PENDING … #define SA5B_INTR_PENDING … #define FIFO_EMPTY … #define HPSA_FIRMWARE_READY … #define HPSA_ERROR_BIT … /* Performant mode flags */ #define SA5_PERF_INTR_PENDING … #define SA5_PERF_INTR_OFF … #define SA5_OUTDB_STATUS_PERF_BIT … #define SA5_OUTDB_CLEAR_PERF_BIT … #define SA5_OUTDB_CLEAR … #define SA5_OUTDB_CLEAR_PERF_BIT … #define SA5_OUTDB_STATUS … #define HPSA_INTR_ON … #define HPSA_INTR_OFF … /* * Inbound Post Queue offsets for IO Accelerator Mode 2 */ #define IOACCEL2_INBOUND_POSTQ_32 … #define IOACCEL2_INBOUND_POSTQ_64_LOW … #define IOACCEL2_INBOUND_POSTQ_64_HI … #define HPSA_PHYSICAL_DEVICE_BUS … #define HPSA_RAID_VOLUME_BUS … #define HPSA_EXTERNAL_RAID_VOLUME_BUS … #define HPSA_HBA_BUS … #define HPSA_LEGACY_HBA_BUS … /* Send the command to the hardware */ static void SA5_submit_command(struct ctlr_info *h, struct CommandList *c) { … } static void SA5_submit_command_no_read(struct ctlr_info *h, struct CommandList *c) { … } static void SA5_submit_command_ioaccel2(struct ctlr_info *h, struct CommandList *c) { … } /* * This card is the opposite of the other cards. * 0 turns interrupts on... * 0x08 turns them off... */ static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) { … } /* * Variant of the above; 0x04 turns interrupts off... */ static void SA5B_intr_mask(struct ctlr_info *h, unsigned long val) { … } static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) { … } static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) { … } /* * returns value read from hardware. * returns FIFO_EMPTY if there is nothing to read */ static unsigned long SA5_completed(struct ctlr_info *h, __attribute__((unused)) u8 q) { … } /* * Returns true if an interrupt is pending.. */ static bool SA5_intr_pending(struct ctlr_info *h) { … } static bool SA5_performant_intr_pending(struct ctlr_info *h) { … } #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT … static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) { … } /* * Returns true if an interrupt is pending.. */ static bool SA5B_intr_pending(struct ctlr_info *h) { … } #define IOACCEL_MODE1_REPLY_QUEUE_INDEX … #define IOACCEL_MODE1_PRODUCER_INDEX … #define IOACCEL_MODE1_CONSUMER_INDEX … #define IOACCEL_MODE1_REPLY_UNUSED … static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) { … } static struct access_method SA5_access = …; /* Duplicate entry of the above to mark unsupported boards */ static struct access_method SA5A_access = …; static struct access_method SA5B_access = …; static struct access_method SA5_ioaccel_mode1_access = …; static struct access_method SA5_ioaccel_mode2_access = …; static struct access_method SA5_performant_access = …; static struct access_method SA5_performant_access_no_read = …; struct board_type { … }; #endif /* HPSA_H */
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