/* SPDX-License-Identifier: GPL-2.0 */ /************************************************************************/ /* */ /* dc395x.h */ /* */ /* Device Driver for Tekram DC395(U/UW/F), DC315(U) */ /* PCI SCSI Bus Master Host Adapter */ /* (SCSI chip set used Tekram ASIC TRM-S1040) */ /* */ /************************************************************************/ #ifndef DC395x_H #define DC395x_H /************************************************************************/ /* */ /* Initial values */ /* */ /************************************************************************/ #define DC395x_MAX_CMD_QUEUE … /* #define DC395x_MAX_QTAGS 32 */ #define DC395x_MAX_QTAGS … #define DC395x_MAX_SCSI_ID … #define DC395x_MAX_CMD_PER_LUN … #define DC395x_MAX_SG_TABLESIZE … #define DC395x_MAX_SG_LISTENTRY … /* item */ #define DC395x_MAX_SRB_CNT … /* #define DC395x_MAX_CAN_QUEUE 7 * DC395x_MAX_QTAGS */ #define DC395x_MAX_CAN_QUEUE … #define DC395x_END_SCAN … #define DC395x_SEL_TIMEOUT … #define DC395x_MAX_RETRIES … #if 0 #define SYNC_FIRST #endif #define NORM_REC_LVL … /************************************************************************/ /* */ /* Various definitions */ /* */ /************************************************************************/ #define BIT31 … #define BIT30 … #define BIT29 … #define BIT28 … #define BIT27 … #define BIT26 … #define BIT25 … #define BIT24 … #define BIT23 … #define BIT22 … #define BIT21 … #define BIT20 … #define BIT19 … #define BIT18 … #define BIT17 … #define BIT16 … #define BIT15 … #define BIT14 … #define BIT13 … #define BIT12 … #define BIT11 … #define BIT10 … #define BIT9 … #define BIT8 … #define BIT7 … #define BIT6 … #define BIT5 … #define BIT4 … #define BIT3 … #define BIT2 … #define BIT1 … #define BIT0 … /* UnitCtrlFlag */ #define UNIT_ALLOCATED … #define UNIT_INFO_CHANGED … #define FORMATING_MEDIA … #define UNIT_RETRY … /* UnitFlags */ #define DASD_SUPPORT … #define SCSI_SUPPORT … #define ASPI_SUPPORT … /* SRBState machine definition */ #define SRB_FREE … #define SRB_WAIT … #define SRB_READY … #define SRB_MSGOUT … #define SRB_MSGIN … #define SRB_EXTEND_MSGIN … #define SRB_COMMAND … #define SRB_START_ … #define SRB_DISCONNECT … #define SRB_DATA_XFER … #define SRB_XFERPAD … #define SRB_STATUS … #define SRB_COMPLETED … #define SRB_ABORT_SENT … #define SRB_DO_SYNC_NEGO … #define SRB_DO_WIDE_NEGO … #define SRB_UNEXPECT_RESEL … /************************************************************************/ /* */ /* ACB Config */ /* */ /************************************************************************/ #define HCC_WIDE_CARD … #define HCC_SCSI_RESET … #define HCC_PARITY … #define HCC_AUTOTERM … #define HCC_LOW8TERM … #define HCC_UP8TERM … /* ACBFlag */ #define RESET_DEV … #define RESET_DETECT … #define RESET_DONE … /* DCBFlag */ #define ABORT_DEV_ … /* SRBstatus */ #define SRB_OK … #define ABORTION … #define OVER_RUN … #define UNDER_RUN … #define PARITY_ERROR … #define SRB_ERROR … /* SRBFlag */ #define DATAOUT … #define DATAIN … #define RESIDUAL_VALID … #define ENABLE_TIMER … #define RESET_DEV0 … #define ABORT_DEV … #define AUTO_REQSENSE … /* Adapter status */ #define H_STATUS_GOOD … #define H_SEL_TIMEOUT … #define H_OVER_UNDER_RUN … #define H_UNEXP_BUS_FREE … #define H_TARGET_PHASE_F … #define H_INVALID_CCB_OP … #define H_LINK_CCB_BAD … #define H_BAD_TARGET_DIR … #define H_DUPLICATE_CCB … #define H_BAD_CCB_OR_SG … #define H_ABORT … /* SCSI BUS Status byte codes */ #define SCSI_STAT_UNEXP_BUS_F … #define SCSI_STAT_BUS_RST_DETECT … #define SCSI_STAT_SEL_TIMEOUT … /* Sync_Mode */ #define SYNC_WIDE_TAG_ATNT_DISABLE … #define SYNC_NEGO_ENABLE … #define SYNC_NEGO_DONE … #define WIDE_NEGO_ENABLE … #define WIDE_NEGO_DONE … #define WIDE_NEGO_STATE … #define EN_TAG_QUEUEING … #define EN_ATN_STOP … #define SYNC_NEGO_OFFSET … /* cmd->result */ #define STATUS_MASK_ … #define MSG_MASK … #define RETURN_MASK … /************************************************************************/ /* */ /* Inquiry Data format */ /* */ /************************************************************************/ struct ScsiInqData { … }; /* Inquiry byte 0 masks */ #define SCSI_DEVTYPE … #define SCSI_PERIPHQUAL … /* Inquiry byte 1 mask */ #define SCSI_REMOVABLE_MEDIA … /* Peripheral Device Type definitions */ /* See include/scsi/scsi.h */ #define TYPE_NODEV … #ifndef TYPE_PRINTER /* */ #define TYPE_PRINTER … #endif /* */ #ifndef TYPE_COMM /* */ #define TYPE_COMM … #endif /************************************************************************/ /* */ /* Inquiry flag definitions (Inq data byte 7) */ /* */ /************************************************************************/ #define SCSI_INQ_RELADR … #define SCSI_INQ_WBUS32 … #define SCSI_INQ_WBUS16 … #define SCSI_INQ_SYNC … #define SCSI_INQ_LINKED … #define SCSI_INQ_CMDQUEUE … #define SCSI_INQ_SFTRE … #define ENABLE_CE … #define DISABLE_CE … #define EEPROM_READ … /************************************************************************/ /* */ /* The PCI configuration register offset for TRM_S1040 */ /* */ /************************************************************************/ #define TRM_S1040_ID … #define TRM_S1040_COMMAND … #define TRM_S1040_IOBASE … #define TRM_S1040_ROMBASE … #define TRM_S1040_INTLINE … /************************************************************************/ /* */ /* The SCSI register offset for TRM_S1040 */ /* */ /************************************************************************/ #define TRM_S1040_SCSI_STATUS … #define COMMANDPHASEDONE … #define SCSIXFERDONE … #define SCSIXFERCNT_2_ZERO … #define SCSIINTERRUPT … #define COMMANDABORT … #define SEQUENCERACTIVE … #define PHASEMISMATCH … #define PARITYERROR … #define PHASEMASK … #define PH_DATA_OUT … #define PH_DATA_IN … #define PH_COMMAND … #define PH_STATUS … #define PH_BUS_FREE … #define PH_MSG_OUT … #define PH_MSG_IN … #define TRM_S1040_SCSI_CONTROL … #define DO_CLRATN … #define DO_SETATN … #define DO_CMDABORT … #define DO_RSTMODULE … #define DO_RSTSCSI … #define DO_CLRFIFO … #define DO_DATALATCH … /* #define DO_DATALATCH 0x0000 */ /* KG: DISable SCSI bus data latch */ #define DO_HWRESELECT … #define TRM_S1040_SCSI_FIFOCNT … #define TRM_S1040_SCSI_SIGNAL … #define TRM_S1040_SCSI_INTSTATUS … #define INT_SCAM … #define INT_SELECT … #define INT_SELTIMEOUT … #define INT_DISCONNECT … #define INT_RESELECTED … #define INT_SCSIRESET … #define INT_BUSSERVICE … #define INT_CMDDONE … #define TRM_S1040_SCSI_OFFSET … /************************************************************************/ /* */ /* Bit Name Definition */ /* --------- ------------- ---------------------------- */ /* 07-05 0 RSVD Reversed. Always 0. */ /* 04 0 OFFSET4 Reversed for LVDS. Always 0. */ /* 03-00 0 OFFSET[03:00] Offset number from 0 to 15 */ /* */ /************************************************************************/ #define TRM_S1040_SCSI_SYNC … #define LVDS_SYNC … #define WIDE_SYNC … #define ALT_SYNC … /************************************************************************/ /* */ /* SYNCM 7 6 5 4 3 2 1 0 */ /* Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0 */ /* Default 0 0 0 0 0 0 0 0 */ /* */ /* Bit Name Definition */ /* --------- ------------- --------------------------- */ /* 07-06 0 RSVD Reversed. Always read 0 */ /* 05 0 LVDS Reversed. Always read 0 */ /* 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI */ /* transfer. */ /* 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode. */ /* */ /* @@ When this bit is set, */ /* the synchronous period bits 2:0 */ /* in the Synchronous Mode register */ /* are used to transfer data */ /* at the Fast-20 rate. */ /* @@ When this bit is unset, */ /* the synchronous period bits 2:0 */ /* in the Synchronous Mode Register */ /* are used to transfer data */ /* at the Fast-10 rate (or Fast-40 w/ LVDS). */ /* */ /* 02-00 0 PERIOD[2:0]/ Synchronous SCSI Transfer Rate. */ /* SXPD[02:00] These 3 bits specify */ /* the Synchronous SCSI Transfer */ /* Rate for Fast-20 and Fast-10. */ /* These bits are also reset */ /* by a SCSI Bus reset. */ /* */ /* For Fast-10 bit ALTPD = 0 and LVDS = 0 */ /* and bit2,bit1,bit0 is defined as follows : */ /* */ /* 000 100ns, 10.0 MHz */ /* 001 150ns, 6.6 MHz */ /* 010 200ns, 5.0 MHz */ /* 011 250ns, 4.0 MHz */ /* 100 300ns, 3.3 MHz */ /* 101 350ns, 2.8 MHz */ /* 110 400ns, 2.5 MHz */ /* 111 450ns, 2.2 MHz */ /* */ /* For Fast-20 bit ALTPD = 1 and LVDS = 0 */ /* and bit2,bit1,bit0 is defined as follows : */ /* */ /* 000 50ns, 20.0 MHz */ /* 001 75ns, 13.3 MHz */ /* 010 100ns, 10.0 MHz */ /* 011 125ns, 8.0 MHz */ /* 100 150ns, 6.6 MHz */ /* 101 175ns, 5.7 MHz */ /* 110 200ns, 5.0 MHz */ /* 111 250ns, 4.0 MHz KG: Maybe 225ns, 4.4 MHz */ /* */ /* For Fast-40 bit ALTPD = 0 and LVDS = 1 */ /* and bit2,bit1,bit0 is defined as follows : */ /* */ /* 000 25ns, 40.0 MHz */ /* 001 50ns, 20.0 MHz */ /* 010 75ns, 13.3 MHz */ /* 011 100ns, 10.0 MHz */ /* 100 125ns, 8.0 MHz */ /* 101 150ns, 6.6 MHz */ /* 110 175ns, 5.7 MHz */ /* 111 200ns, 5.0 MHz */ /* */ /************************************************************************/ #define TRM_S1040_SCSI_TARGETID … #define TRM_S1040_SCSI_IDMSG … #define TRM_S1040_SCSI_HOSTID … #define TRM_S1040_SCSI_COUNTER … #define TRM_S1040_SCSI_INTEN … #define EN_SCAM … #define EN_SELECT … #define EN_SELTIMEOUT … #define EN_DISCONNECT … #define EN_RESELECTED … #define EN_SCSIRESET … #define EN_BUSSERVICE … #define EN_CMDDONE … #define TRM_S1040_SCSI_CONFIG0 … #define PHASELATCH … #define INITIATOR … #define PARITYCHECK … #define BLOCKRST … #define TRM_S1040_SCSI_CONFIG1 … #define ACTIVE_NEGPLUS … #define FILTER_DISABLE … #define FAST_FILTER … #define ACTIVE_NEG … #define TRM_S1040_SCSI_CONFIG2 … #define CFG2_WIDEFIFO … #define TRM_S1040_SCSI_COMMAND … #define SCMD_COMP … #define SCMD_SEL_ATN … #define SCMD_SEL_ATN3 … #define SCMD_SEL_ATNSTOP … #define SCMD_FIFO_OUT … #define SCMD_DMA_OUT … #define SCMD_FIFO_IN … #define SCMD_DMA_IN … #define SCMD_MSGACCEPT … /************************************************************************/ /* */ /* Code Command Description */ /* ---- ---------------------------------------- */ /* 02 Enable reselection with FIFO */ /* 40 Select without ATN with FIFO */ /* 60 Select with ATN with FIFO */ /* 64 Select with ATN3 with FIFO */ /* A0 Select with ATN and stop with FIFO */ /* C0 Transfer information out with FIFO */ /* C1 Transfer information out with DMA */ /* C2 Transfer information in with FIFO */ /* C3 Transfer information in with DMA */ /* 12 Initiator command complete with FIFO */ /* 50 Initiator transfer information out sequence without ATN */ /* with FIFO */ /* 70 Initiator transfer information out sequence with ATN */ /* with FIFO */ /* 74 Initiator transfer information out sequence with ATN3 */ /* with FIFO */ /* 52 Initiator transfer information in sequence without ATN */ /* with FIFO */ /* 72 Initiator transfer information in sequence with ATN */ /* with FIFO */ /* 76 Initiator transfer information in sequence with ATN3 */ /* with FIFO */ /* 90 Initiator transfer information out command complete */ /* with FIFO */ /* 92 Initiator transfer information in command complete */ /* with FIFO */ /* D2 Enable selection */ /* 08 Reselection */ /* 48 Disconnect command with FIFO */ /* 88 Terminate command with FIFO */ /* C8 Target command complete with FIFO */ /* 18 SCAM Arbitration/ Selection */ /* 5A Enable reselection */ /* 98 Select without ATN with FIFO */ /* B8 Select with ATN with FIFO */ /* D8 Message Accepted */ /* 58 NOP */ /* */ /************************************************************************/ #define TRM_S1040_SCSI_TIMEOUT … #define TRM_S1040_SCSI_FIFO … #define TRM_S1040_SCSI_TCR0 … #define TCR0_WIDE_NEGO_DONE … #define TCR0_SYNC_NEGO_DONE … #define TCR0_ENABLE_LVDS … #define TCR0_ENABLE_WIDE … #define TCR0_ENABLE_ALT … #define TCR0_PERIOD_MASK … #define TCR0_DO_WIDE_NEGO … #define TCR0_DO_SYNC_NEGO … #define TCR0_DISCONNECT_EN … #define TCR0_OFFSET_MASK … #define TRM_S1040_SCSI_TCR1 … #define MAXTAG_MASK … #define NON_TAG_BUSY … #define ACTTAG_MASK … /************************************************************************/ /* */ /* The DMA register offset for TRM_S1040 */ /* */ /************************************************************************/ #define TRM_S1040_DMA_COMMAND … #define DMACMD_SG … #define DMACMD_DIR … #define XFERDATAIN_SG … #define XFERDATAOUT_SG … #define XFERDATAIN … #define XFERDATAOUT … #define TRM_S1040_DMA_FIFOCNT … #define TRM_S1040_DMA_CONTROL … #define DMARESETMODULE … #define STOPDMAXFER … #define ABORTXFER … #define CLRXFIFO … #define STARTDMAXFER … #define TRM_S1040_DMA_FIFOSTAT … #define TRM_S1040_DMA_STATUS … #define XFERPENDING … #define SCSIBUSY … #define GLOBALINT … #define FORCEDMACOMP … #define DMAXFERERROR … #define DMAXFERABORT … #define DMAXFERCOMP … #define SCSICOMP … #define TRM_S1040_DMA_INTEN … #define EN_FORCEDMACOMP … #define EN_DMAXFERERROR … #define EN_DMAXFERABORT … #define EN_DMAXFERCOMP … #define EN_SCSIINTR … #define TRM_S1040_DMA_CONFIG … #define DMA_ENHANCE … #define DMA_PCI_DUAL_ADDR … #define DMA_CFG_RES … #define DMA_AUTO_CLR_FIFO … #define DMA_MEM_MULTI_READ … #define DMA_MEM_WRITE_INVAL … #define DMA_FIFO_CTRL … #define DMA_FIFO_HALF_HALF … #define TRM_S1040_DMA_XCNT … #define TRM_S1040_DMA_CXCNT … #define TRM_S1040_DMA_XLOWADDR … #define TRM_S1040_DMA_XHIGHADDR … /************************************************************************/ /* */ /* The general register offset for TRM_S1040 */ /* */ /************************************************************************/ #define TRM_S1040_GEN_CONTROL … #define CTRL_LED … #define EN_EEPROM … #define DIS_TERM … #define AUTOTERM … #define LOW8TERM … #define UP8TERM … #define TRM_S1040_GEN_STATUS … #define GTIMEOUT … #define EXT68HIGH … #define INT68HIGH … #define CON5068 … #define CON68 … #define CON50 … #define WIDESCSI … #define STATUS_LOAD_DEFAULT … #define TRM_S1040_GEN_NVRAM … #define NVR_BITOUT … #define NVR_BITIN … #define NVR_CLOCK … #define NVR_SELECT … #define TRM_S1040_GEN_EDATA … #define TRM_S1040_GEN_EADDRESS … #define TRM_S1040_GEN_TIMER … /************************************************************************/ /* */ /* NvmTarCfg0: Target configuration byte 0 :..pDCB->DevMode */ /* */ /************************************************************************/ #define NTC_DO_WIDE_NEGO … #define NTC_DO_TAG_QUEUEING … #define NTC_DO_SEND_START … #define NTC_DO_DISCONNECT … #define NTC_DO_SYNC_NEGO … #define NTC_DO_PARITY_CHK … /* Parity check enable */ /************************************************************************/ /* */ /* Nvram Initiater bits definition */ /* */ /************************************************************************/ #if 0 #define MORE2_DRV … #define GREATER_1G … #define RST_SCSI_BUS … #define ACTIVE_NEGATION … #define NO_SEEK … #define LUN_CHECK … #endif /************************************************************************/ /* */ /* Nvram Adapter Cfg bits definition */ /* */ /************************************************************************/ #define NAC_SCANLUN … #define NAC_POWERON_SCSI_RESET … #define NAC_GREATER_1G … #define NAC_GT2DRIVES … /* #define NAC_DO_PARITY_CHK 0x08 */ /* Parity check enable */ #endif
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