/* SPDX-License-Identifier: GPL-2.0 */ /* esp_scsi.h: Defines and structures for the ESP driver. * * Copyright (C) 2007 David S. Miller ([email protected]) */ #ifndef _ESP_SCSI_H #define _ESP_SCSI_H /* Access Description Offset */ #define ESP_TCLOW … #define ESP_TCMED … #define ESP_FDATA … #define ESP_CMD … #define ESP_STATUS … #define ESP_BUSID … #define ESP_INTRPT … #define ESP_TIMEO … #define ESP_SSTEP … #define ESP_STP … #define ESP_FFLAGS … #define ESP_SOFF … #define ESP_CFG1 … #define ESP_CFACT … #define ESP_STATUS2 … #define ESP_CTEST … #define ESP_CFG2 … #define ESP_CFG3 … #define ESP_CFG4 … #define ESP_TCHI … #define ESP_UID … #define FAS_RLO … #define ESP_FGRND … #define FAS_RHI … #define SBUS_ESP_REG_SIZE … /* Bitfield meanings for the above registers. */ /* ESP config reg 1, read-write, found on all ESP chips */ #define ESP_CONFIG1_ID … #define ESP_CONFIG1_CHTEST … #define ESP_CONFIG1_PENABLE … #define ESP_CONFIG1_PARTEST … #define ESP_CONFIG1_SRRDISAB … #define ESP_CONFIG1_SLCABLE … /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */ #define ESP_CONFIG2_DMAPARITY … #define ESP_CONFIG2_REGPARITY … #define ESP_CONFIG2_BADPARITY … #define ESP_CONFIG2_SCSI2ENAB … #define ESP_CONFIG2_HI … #define ESP_CONFIG2_HMEFENAB … #define ESP_CONFIG2_BCM … #define ESP_CONFIG2_DISPINT … #define ESP_CONFIG2_FENAB … #define ESP_CONFIG2_SPL … #define ESP_CONFIG2_MKDONE … #define ESP_CONFIG2_HME32 … #define ESP_CONFIG2_MAGIC … /* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */ #define ESP_CONFIG3_FCLOCK … #define ESP_CONFIG3_TEM … #define ESP_CONFIG3_FAST … #define ESP_CONFIG3_ADMA … #define ESP_CONFIG3_TENB … #define ESP_CONFIG3_SRB … #define ESP_CONFIG3_TMS … #define ESP_CONFIG3_FCLK … #define ESP_CONFIG3_IDMSG … #define ESP_CONFIG3_FSCSI … #define ESP_CONFIG3_GTM … #define ESP_CONFIG3_IDBIT3 … #define ESP_CONFIG3_TBMS … #define ESP_CONFIG3_EWIDE … #define ESP_CONFIG3_IMS … #define ESP_CONFIG3_OBPUSH … /* ESP config register 4 read-write */ #define ESP_CONFIG4_BBTE … #define ESP_CONGIG4_TEST … #define ESP_CONFIG4_RADE … #define ESP_CONFIG4_RAE … #define ESP_CONFIG4_PWD … #define ESP_CONFIG4_GE0 … #define ESP_CONFIG4_GE1 … #define ESP_CONFIG_GE_12NS … #define ESP_CONFIG_GE_25NS … #define ESP_CONFIG_GE_35NS … #define ESP_CONFIG_GE_0NS … /* ESP command register read-write */ /* Group 1 commands: These may be sent at any point in time to the ESP * chip. None of them can generate interrupts 'cept * the "SCSI bus reset" command if you have not disabled * SCSI reset interrupts in the config1 ESP register. */ #define ESP_CMD_NULL … #define ESP_CMD_FLUSH … #define ESP_CMD_RC … #define ESP_CMD_RS … /* Group 2 commands: ESP must be an initiator and connected to a target * for these commands to work. */ #define ESP_CMD_TI … #define ESP_CMD_ICCSEQ … #define ESP_CMD_MOK … #define ESP_CMD_TPAD … #define ESP_CMD_SATN … #define ESP_CMD_RATN … /* Group 3 commands: ESP must be in the MSGOUT or MSGIN state and be connected * to a target as the initiator for these commands to work. */ #define ESP_CMD_SMSG … #define ESP_CMD_SSTAT … #define ESP_CMD_SDATA … #define ESP_CMD_DSEQ … #define ESP_CMD_TSEQ … #define ESP_CMD_TCCSEQ … #define ESP_CMD_DCNCT … #define ESP_CMD_RMSG … #define ESP_CMD_RCMD … #define ESP_CMD_RDATA … #define ESP_CMD_RCSEQ … /* Group 4 commands: The ESP must be in the disconnected state and must * not be connected to any targets as initiator for * these commands to work. */ #define ESP_CMD_RSEL … #define ESP_CMD_SEL … #define ESP_CMD_SELA … #define ESP_CMD_SELAS … #define ESP_CMD_ESEL … #define ESP_CMD_DSEL … #define ESP_CMD_SA3 … #define ESP_CMD_RSEL3 … /* This bit enables the ESP's DMA on the SBus */ #define ESP_CMD_DMA … /* ESP status register read-only */ #define ESP_STAT_PIO … #define ESP_STAT_PCD … #define ESP_STAT_PMSG … #define ESP_STAT_PMASK … #define ESP_STAT_TDONE … #define ESP_STAT_TCNT … #define ESP_STAT_PERR … #define ESP_STAT_SPAM … /* This indicates the 'interrupt pending' condition on esp236, it is a reserved * bit on other revs of the ESP. */ #define ESP_STAT_INTR … /* The status register can be masked with ESP_STAT_PMASK and compared * with the following values to determine the current phase the ESP * (at least thinks it) is in. For our purposes we also add our own * software 'done' bit for our phase management engine. */ #define ESP_DOP … #define ESP_DIP … #define ESP_CMDP … #define ESP_STATP … #define ESP_MOP … #define ESP_MIP … /* HME only: status 2 register */ #define ESP_STAT2_SCHBIT … #define ESP_STAT2_FFLAGS … #define ESP_STAT2_XCNT … #define ESP_STAT2_CREGA … #define ESP_STAT2_WIDE … #define ESP_STAT2_F1BYTE … #define ESP_STAT2_FMSB … #define ESP_STAT2_FEMPTY … /* ESP interrupt register read-only */ #define ESP_INTR_S … #define ESP_INTR_SATN … #define ESP_INTR_RSEL … #define ESP_INTR_FDONE … #define ESP_INTR_BSERV … #define ESP_INTR_DC … #define ESP_INTR_IC … #define ESP_INTR_SR … /* ESP sequence step register read-only */ #define ESP_STEP_VBITS … #define ESP_STEP_ASEL … #define ESP_STEP_SID … #define ESP_STEP_NCMD … #define ESP_STEP_PPC … #define ESP_STEP_FINI4 … /* Ho hum, some ESP's set the step register to this as well... */ #define ESP_STEP_FINI5 … #define ESP_STEP_FINI6 … #define ESP_STEP_FINI7 … /* ESP chip-test register read-write */ #define ESP_TEST_TARG … #define ESP_TEST_INI … #define ESP_TEST_TS … /* ESP unique ID register read-only, found on fas236+fas100a only */ #define ESP_UID_FAM … #define ESP_FAMILY(uid) … /* Values for the ESP family bits */ #define ESP_UID_F100A … #define ESP_UID_F236 … #define ESP_UID_HME … #define ESP_UID_FSC … /* ESP fifo flags register read-only */ /* Note that the following implies a 16 byte FIFO on the ESP. */ #define ESP_FF_FBYTES … #define ESP_FF_ONOTZERO … #define ESP_FF_SSTEP … /* ESP clock conversion factor register write-only */ #define ESP_CCF_F0 … #define ESP_CCF_NEVER … #define ESP_CCF_F2 … #define ESP_CCF_F3 … #define ESP_CCF_F4 … #define ESP_CCF_F5 … #define ESP_CCF_F6 … #define ESP_CCF_F7 … /* HME only... */ #define ESP_BUSID_RESELID … #define ESP_BUSID_CTR32BIT … #define ESP_BUS_TIMEOUT … #define ESP_TIMEO_CONST … #define ESP_NEG_DEFP(mhz, cfact) … #define ESP_HZ_TO_CYCLE(hertz) … #define ESP_TICK(ccf, cycle) … /* For slow to medium speed input clock rates we shoot for 5mb/s, but for high * input clock rates we try to do 10mb/s although I don't think a transfer can * even run that fast with an ESP even with DMA2 scatter gather pipelining. */ #define SYNC_DEFP_SLOW … #define SYNC_DEFP_FAST … struct esp_cmd_priv { … }; #define ESP_CMD_PRIV(cmd) … /* NOTE: this enum is ordered based on chip features! */ enum esp_rev { … }; struct esp_cmd_entry { … }; #define ESP_DEFAULT_TAGS … #define ESP_MAX_TARGET … #define ESP_MAX_LUN … #define ESP_MAX_TAG … struct esp_lun_data { … }; struct esp_target_data { … }; struct esp_event_ent { … }; struct esp; struct esp_driver_ops { … }; #define ESP_MAX_MSG_SZ … #define ESP_EVENT_LOG_SZ … #define ESP_QUICKIRQ_LIMIT … #define ESP_RESELECT_TAG_LIMIT … struct esp { … }; /* A front-end driver for the ESP chip should do the following in * it's device probe routine: * 1) Allocate the host and private area using scsi_host_alloc() * with size 'sizeof(struct esp)'. The first argument to * scsi_host_alloc() should be &scsi_esp_template. * 2) Set host->max_id as appropriate. * 3) Set esp->host to the scsi_host itself, and esp->dev * to the device object pointer. * 4) Hook up esp->ops to the front-end implementation. * 5) If the ESP chip supports wide transfers, set ESP_FLAG_WIDE_CAPABLE * in esp->flags. * 6) Map the DMA and ESP chip registers. * 7) DMA map the ESP command block, store the DMA address * in esp->command_block_dma. * 8) Register the scsi_esp_intr() interrupt handler. * 9) Probe for and provide the following chip properties: * esp->scsi_id (assign to esp->host->this_id too) * esp->scsi_id_mask * If ESP bus is differential, set ESP_FLAG_DIFFERENTIAL * esp->cfreq * DMA burst bit mask in esp->bursts, if necessary * 10) Perform any actions necessary before the ESP device can * be programmed for the first time. On some configs, for * example, the DMA engine has to be reset before ESP can * be programmed. * 11) If necessary, call dev_set_drvdata() as needed. * 12) Call scsi_esp_register() with prepared 'esp' structure. * 13) Check scsi_esp_register() return value, release all resources * if an error was returned. */ extern const struct scsi_host_template scsi_esp_template; extern int scsi_esp_register(struct esp *); extern void scsi_esp_unregister(struct esp *); extern irqreturn_t scsi_esp_intr(int, void *); extern void scsi_esp_cmd(struct esp *, u8); extern void esp_send_pio_cmd(struct esp *esp, u32 dma_addr, u32 esp_count, u32 dma_count, int write, u8 cmd); #endif /* !(_ESP_SCSI_H) */
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