/* SPDX-License-Identifier: GPL-2.0 */ /* * Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers * * Copyright 2017 Hannes Reinecke, SUSE Linux GmbH <[email protected]> * * Based on the original DAC960 driver, * Copyright 1998-2001 by Leonard N. Zubkoff <[email protected]> * Portions Copyright 2002 by Mylex (An IBM Business Unit) * */ #ifndef MYRB_H #define MYRB_H #define MYRB_MAX_LDEVS … #define MYRB_MAX_CHANNELS … #define MYRB_MAX_TARGETS … #define MYRB_MAX_PHYSICAL_DEVICES … #define MYRB_SCATTER_GATHER_LIMIT … #define MYRB_CMD_MBOX_COUNT … #define MYRB_STAT_MBOX_COUNT … #define MYRB_BLKSIZE_BITS … #define MYRB_MAILBOX_TIMEOUT … #define MYRB_DCMD_TAG … #define MYRB_MCMD_TAG … #define MYRB_PRIMARY_MONITOR_INTERVAL … #define MYRB_SECONDARY_MONITOR_INTERVAL … /* * DAC960 V1 Firmware Command Opcodes. */ enum myrb_cmd_opcode { … } __packed; /* * DAC960 V1 Firmware Command Status Codes. */ #define MYRB_STATUS_SUCCESS … #define MYRB_STATUS_CHECK_CONDITION … #define MYRB_STATUS_NO_DEVICE … #define MYRB_STATUS_INVALID_ADDRESS … #define MYRB_STATUS_INVALID_PARAM … #define MYRB_STATUS_IRRECOVERABLE_DATA_ERROR … #define MYRB_STATUS_LDRV_NONEXISTENT_OR_OFFLINE … #define MYRB_STATUS_ACCESS_BEYOND_END_OF_LDRV … #define MYRB_STATUS_BAD_DATA … #define MYRB_STATUS_DEVICE_BUSY … #define MYRB_STATUS_DEVICE_NONRESPONSIVE … #define MYRB_STATUS_COMMAND_TERMINATED … #define MYRB_STATUS_START_DEVICE_FAILED … #define MYRB_STATUS_INVALID_CHANNEL_OR_TARGET … #define MYRB_STATUS_CHANNEL_BUSY … #define MYRB_STATUS_OUT_OF_MEMORY … #define MYRB_STATUS_CHANNEL_NOT_STOPPED … #define MYRB_STATUS_ATTEMPT_TO_RBLD_ONLINE_DRIVE … #define MYRB_STATUS_RBLD_BADBLOCKS … #define MYRB_STATUS_RBLD_NEW_DISK_FAILED … #define MYRB_STATUS_RBLD_OR_CHECK_INPROGRESS … #define MYRB_STATUS_DEPENDENT_DISK_DEAD … #define MYRB_STATUS_INCONSISTENT_BLOCKS … #define MYRB_STATUS_INVALID_OR_NONREDUNDANT_LDRV … #define MYRB_STATUS_NO_RBLD_OR_CHECK_INPROGRESS … #define MYRB_STATUS_RBLD_IN_PROGRESS_DATA_VALID … #define MYRB_STATUS_RBLD_FAILED_LDEV_FAILURE … #define MYRB_STATUS_RBLD_FAILED_BADBLOCKS … #define MYRB_STATUS_RBLD_FAILED_NEW_DRIVE_FAILED … #define MYRB_STATUS_RBLD_SUCCESS … #define MYRB_STATUS_RBLD_SUCCESS_TERMINATED … #define MYRB_STATUS_RBLD_NOT_CHECKED … #define MYRB_STATUS_BGI_SUCCESS … #define MYRB_STATUS_BGI_ABORTED … #define MYRB_STATUS_NO_BGI_INPROGRESS … #define MYRB_STATUS_ADD_CAPACITY_INPROGRESS … #define MYRB_STATUS_ADD_CAPACITY_FAILED_OR_SUSPENDED … #define MYRB_STATUS_CONFIG2_CSUM_ERROR … #define MYRB_STATUS_CONFIGURATION_SUSPENDED … #define MYRB_STATUS_FAILED_TO_CONFIGURE_NVRAM … #define MYRB_STATUS_CONFIGURATION_NOT_SAVED … #define MYRB_STATUS_SUBSYS_NOTINSTALLED … #define MYRB_STATUS_SUBSYS_FAILED … #define MYRB_STATUS_SUBSYS_BUSY … #define MYRB_STATUS_SUBSYS_TIMEOUT … /* * DAC960 V1 Firmware Enquiry Command reply structure. */ struct myrb_enquiry { … } __packed; /* * DAC960 V1 Firmware Enquiry2 Command reply structure. */ struct myrb_enquiry2 { … } __packed; /* * DAC960 V1 Firmware Logical Drive State type. */ enum myrb_devstate { … } __packed; /* * DAC960 V1 RAID Levels */ enum myrb_raidlevel { … } __packed; /* * DAC960 V1 Firmware Logical Drive Information structure. */ struct myrb_ldev_info { … }; /* * DAC960 V1 Firmware Perform Event Log Operation Types. */ #define DAC960_V1_GetEventLogEntry … /* * DAC960 V1 Firmware Get Event Log Entry Command reply structure. */ struct myrb_log_entry { … }; /* * DAC960 V1 Firmware Get Device State Command reply structure. * The structure is padded by 2 bytes for compatibility with Version 2.xx * Firmware. */ struct myrb_pdev_state { … } __packed; /* * DAC960 V1 Firmware Get Rebuild Progress Command reply structure. */ struct myrb_rbld_progress { … }; /* * DAC960 V1 Firmware Background Initialization Status Command reply structure. */ struct myrb_bgi_status { … }; /* * DAC960 V1 Firmware Error Table Entry structure. */ struct myrb_error_entry { … }; /* * DAC960 V1 Firmware Read Config2 Command reply structure. */ struct myrb_config2 { … }; /* * DAC960 V1 Firmware DCDB request structure. */ struct myrb_dcdb { … }; /* * DAC960 V1 Firmware Scatter/Gather List Type 1 32 Bit Address *32 Bit Byte Count structure. */ struct myrb_sge { … }; /* * 13 Byte DAC960 V1 Firmware Command Mailbox structure. * Bytes 13-15 are not used. The structure is padded to 16 bytes for * efficient access. */ myrb_cmd_mbox; /* * DAC960 V1 Firmware Controller Status Mailbox structure. */ struct myrb_stat_mbox { … }; struct myrb_cmdblk { … }; struct myrb_hba { … }; /* * DAC960 LA Series Controller Interface Register Offsets. */ #define DAC960_LA_mmio_size … enum DAC960_LA_reg_offset { … }; /* * DAC960 LA Series Inbound Door Bell Register. */ #define DAC960_LA_IDB_HWMBOX_NEW_CMD … #define DAC960_LA_IDB_HWMBOX_ACK_STS … #define DAC960_LA_IDB_GEN_IRQ … #define DAC960_LA_IDB_CTRL_RESET … #define DAC960_LA_IDB_MMBOX_NEW_CMD … #define DAC960_LA_IDB_HWMBOX_EMPTY … #define DAC960_LA_IDB_INIT_DONE … /* * DAC960 LA Series Outbound Door Bell Register. */ #define DAC960_LA_ODB_HWMBOX_ACK_IRQ … #define DAC960_LA_ODB_MMBOX_ACK_IRQ … #define DAC960_LA_ODB_HWMBOX_STS_AVAIL … #define DAC960_LA_ODB_MMBOX_STS_AVAIL … /* * DAC960 LA Series Interrupt Mask Register. */ #define DAC960_LA_IRQMASK_DISABLE_IRQ … /* * DAC960 LA Series Error Status Register. */ #define DAC960_LA_ERRSTS_PENDING … /* * DAC960 PG Series Controller Interface Register Offsets. */ #define DAC960_PG_mmio_size … enum DAC960_PG_reg_offset { … }; /* * DAC960 PG Series Inbound Door Bell Register. */ #define DAC960_PG_IDB_HWMBOX_NEW_CMD … #define DAC960_PG_IDB_HWMBOX_ACK_STS … #define DAC960_PG_IDB_GEN_IRQ … #define DAC960_PG_IDB_CTRL_RESET … #define DAC960_PG_IDB_MMBOX_NEW_CMD … #define DAC960_PG_IDB_HWMBOX_FULL … #define DAC960_PG_IDB_INIT_IN_PROGRESS … /* * DAC960 PG Series Outbound Door Bell Register. */ #define DAC960_PG_ODB_HWMBOX_ACK_IRQ … #define DAC960_PG_ODB_MMBOX_ACK_IRQ … #define DAC960_PG_ODB_HWMBOX_STS_AVAIL … #define DAC960_PG_ODB_MMBOX_STS_AVAIL … /* * DAC960 PG Series Interrupt Mask Register. */ #define DAC960_PG_IRQMASK_MSI_MASK1 … #define DAC960_PG_IRQMASK_DISABLE_IRQ … #define DAC960_PG_IRQMASK_MSI_MASK2 … /* * DAC960 PG Series Error Status Register. */ #define DAC960_PG_ERRSTS_PENDING … /* * DAC960 PD Series Controller Interface Register Offsets. */ #define DAC960_PD_mmio_size … enum DAC960_PD_reg_offset { … }; /* * DAC960 PD Series Inbound Door Bell Register. */ #define DAC960_PD_IDB_HWMBOX_NEW_CMD … #define DAC960_PD_IDB_HWMBOX_ACK_STS … #define DAC960_PD_IDB_GEN_IRQ … #define DAC960_PD_IDB_CTRL_RESET … #define DAC960_PD_IDB_HWMBOX_FULL … #define DAC960_PD_IDB_INIT_IN_PROGRESS … /* * DAC960 PD Series Outbound Door Bell Register. */ #define DAC960_PD_ODB_HWMBOX_ACK_IRQ … #define DAC960_PD_ODB_HWMBOX_STS_AVAIL … /* * DAC960 PD Series Interrupt Enable Register. */ #define DAC960_PD_IRQMASK_ENABLE_IRQ … /* * DAC960 PD Series Error Status Register. */ #define DAC960_PD_ERRSTS_PENDING … myrb_hw_init_t; mbox_mmio_init_t; struct myrb_privdata { … }; #endif /* MYRB_H */
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