/* 3w-xxxx.h -- 3ware Storage Controller device driver for Linux. Written By: Adam Radford <[email protected]> Modifications By: Joel Jacobson <[email protected]> Arnaldo Carvalho de Melo <[email protected]> Brad Strand <[email protected]> Copyright (C) 1999-2010 3ware Inc. Kernel compatibility By: Andre Hedrick <[email protected]> Non-Copyright (C) 2000 Andre Hedrick <[email protected]> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; version 2 of the License. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. NO WARRANTY THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is solely responsible for determining the appropriateness of using and distributing the Program and assumes all risks associated with its exercise of rights under this Agreement, including but not limited to the risks and costs of program errors, damage to or loss of data, programs or equipment, and unavailability or interruption of operations. DISCLAIMER OF LIABILITY NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Bugs/Comments/Suggestions should be mailed to: [email protected] For more information, goto: http://www.lsi.com */ #ifndef _3W_XXXX_H #define _3W_XXXX_H #include <linux/types.h> /* AEN strings */ static char *tw_aen_string[] = …; /* Sense key lookup table Format: ESDC/flags,SenseKey,AdditionalSenseCode,AdditionalSenseCodeQualifier */ static unsigned char tw_sense_table[][4] = …; /* Control register bit definitions */ #define TW_CONTROL_CLEAR_HOST_INTERRUPT … #define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT … #define TW_CONTROL_MASK_COMMAND_INTERRUPT … #define TW_CONTROL_MASK_RESPONSE_INTERRUPT … #define TW_CONTROL_UNMASK_COMMAND_INTERRUPT … #define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT … #define TW_CONTROL_CLEAR_ERROR_STATUS … #define TW_CONTROL_ISSUE_SOFT_RESET … #define TW_CONTROL_ENABLE_INTERRUPTS … #define TW_CONTROL_DISABLE_INTERRUPTS … #define TW_CONTROL_ISSUE_HOST_INTERRUPT … #define TW_CONTROL_CLEAR_PARITY_ERROR … #define TW_CONTROL_CLEAR_QUEUE_ERROR … #define TW_CONTROL_CLEAR_PCI_ABORT … #define TW_CONTROL_CLEAR_SBUF_WRITE_ERROR … /* Status register bit definitions */ #define TW_STATUS_MAJOR_VERSION_MASK … #define TW_STATUS_MINOR_VERSION_MASK … #define TW_STATUS_PCI_PARITY_ERROR … #define TW_STATUS_QUEUE_ERROR … #define TW_STATUS_MICROCONTROLLER_ERROR … #define TW_STATUS_PCI_ABORT … #define TW_STATUS_HOST_INTERRUPT … #define TW_STATUS_ATTENTION_INTERRUPT … #define TW_STATUS_COMMAND_INTERRUPT … #define TW_STATUS_RESPONSE_INTERRUPT … #define TW_STATUS_COMMAND_QUEUE_FULL … #define TW_STATUS_RESPONSE_QUEUE_EMPTY … #define TW_STATUS_MICROCONTROLLER_READY … #define TW_STATUS_COMMAND_QUEUE_EMPTY … #define TW_STATUS_ALL_INTERRUPTS … #define TW_STATUS_CLEARABLE_BITS … #define TW_STATUS_EXPECTED_BITS … #define TW_STATUS_UNEXPECTED_BITS … #define TW_STATUS_SBUF_WRITE_ERROR … #define TW_STATUS_VALID_INTERRUPT … /* RESPONSE QUEUE BIT DEFINITIONS */ #define TW_RESPONSE_ID_MASK … /* PCI related defines */ #define TW_IO_ADDRESS_RANGE … #define TW_DEVICE_NAME … #define TW_VENDOR_ID … #define TW_DEVICE_ID … #define TW_DEVICE_ID2 … #define TW_NUMDEVICES … #define TW_PCI_CLEAR_PARITY_ERRORS … #define TW_PCI_CLEAR_PCI_ABORT … /* Command packet opcodes */ #define TW_OP_NOP … #define TW_OP_INIT_CONNECTION … #define TW_OP_READ … #define TW_OP_WRITE … #define TW_OP_VERIFY … #define TW_OP_GET_PARAM … #define TW_OP_SET_PARAM … #define TW_OP_SECTOR_INFO … #define TW_OP_AEN_LISTEN … #define TW_OP_FLUSH_CACHE … #define TW_CMD_PACKET … #define TW_CMD_PACKET_WITH_DATA … /* Asynchronous Event Notification (AEN) Codes */ #define TW_AEN_QUEUE_EMPTY … #define TW_AEN_SOFT_RESET … #define TW_AEN_DEGRADED_MIRROR … #define TW_AEN_CONTROLLER_ERROR … #define TW_AEN_REBUILD_FAIL … #define TW_AEN_REBUILD_DONE … #define TW_AEN_QUEUE_FULL … #define TW_AEN_TABLE_UNDEFINED … #define TW_AEN_APORT_TIMEOUT … #define TW_AEN_DRIVE_ERROR … #define TW_AEN_SMART_FAIL … #define TW_AEN_SBUF_FAIL … /* Misc defines */ #define TW_ALIGNMENT_6000 … #define TW_ALIGNMENT_7000 … #define TW_MAX_UNITS … #define TW_COMMAND_ALIGNMENT_MASK … #define TW_INIT_MESSAGE_CREDITS … #define TW_INIT_COMMAND_PACKET_SIZE … #define TW_POLL_MAX_RETRIES … #define TW_MAX_SGL_LENGTH … #define TW_ATA_PASS_SGL_MAX … #define TW_Q_LENGTH … #define TW_Q_START … #define TW_MAX_SLOT … #define TW_MAX_PCI_BUSES … #define TW_MAX_RESET_TRIES … #define TW_UNIT_INFORMATION_TABLE_BASE … #define TW_MAX_CMDS_PER_LUN … #define TW_BLOCK_SIZE … #define TW_IOCTL … #define TW_UNIT_ONLINE … #define TW_IN_INTR … #define TW_IN_RESET … #define TW_IN_CHRDEV_IOCTL … #define TW_MAX_SECTORS … #define TW_MAX_IOCTL_SECTORS … #define TW_AEN_WAIT_TIME … #define TW_IOCTL_WAIT_TIME … #define TW_ISR_DONT_COMPLETE … #define TW_ISR_DONT_RESULT … #define TW_IOCTL_TIMEOUT … #define TW_IOCTL_CHRDEV_TIMEOUT … #define TW_IOCTL_CHRDEV_FREE … #define TW_MAX_CDB_LEN … /* Bitmask macros to eliminate bitfields */ /* opcode: 5, sgloffset: 3 */ #define TW_OPSGL_IN(x,y) … #define TW_SGL_OUT(x) … /* reserved_1: 4, response_id: 8, reserved_2: 20 */ #define TW_RESID_OUT(x) … /* unit: 4, host_id: 4 */ #define TW_UNITHOST_IN(x,y) … #define TW_UNIT_OUT(x) … /* Macros */ #define TW_CONTROL_REG_ADDR(x) … #define TW_STATUS_REG_ADDR(x) … #define TW_COMMAND_QUEUE_REG_ADDR(x) … #define TW_RESPONSE_QUEUE_REG_ADDR(x) … #define TW_CLEAR_ALL_INTERRUPTS(x) … #define TW_CLEAR_ATTENTION_INTERRUPT(x) … #define TW_CLEAR_HOST_INTERRUPT(x) … #define TW_DISABLE_INTERRUPTS(x) … #define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) … #define TW_MASK_COMMAND_INTERRUPT(x) … #define TW_UNMASK_COMMAND_INTERRUPT(x) … #define TW_SOFT_RESET(x) … #define TW_STATUS_ERRORS(x) … #ifdef TW_DEBUG #define dprintk … #else #define dprintk(msg...) … #endif #pragma pack(1) /* Scatter Gather List Entry */ TW_SG_Entry; TW_Sector; /* Command Packet */ TW_Command; #pragma pack() TW_Ioctl; #pragma pack(1) /* Structure for new chardev ioctls */ TW_New_Ioctl; /* GetParam descriptor */ PTW_Param; /* Response queue */ TW_Response_Queue; TW_Cmd_State; #define TW_S_INITIAL … #define TW_S_STARTED … #define TW_S_POSTED … #define TW_S_PENDING … #define TW_S_COMPLETED … #define TW_S_FINISHED … #define TW_START_MASK … /* Command header for ATA pass-thru */ TW_Passthru; #pragma pack() TW_Device_Extension; #endif /* _3W_XXXX_H */
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