/* 3w-9xxx.h -- 3ware 9000 Storage Controller device driver for Linux. Written By: Adam Radford <[email protected]> Modifications By: Tom Couch Copyright (C) 2004-2009 Applied Micro Circuits Corporation. Copyright (C) 2010 LSI Corporation. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; version 2 of the License. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. NO WARRANTY THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is solely responsible for determining the appropriateness of using and distributing the Program and assumes all risks associated with its exercise of rights under this Agreement, including but not limited to the risks and costs of program errors, damage to or loss of data, programs or equipment, and unavailability or interruption of operations. DISCLAIMER OF LIABILITY NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Bugs/Comments/Suggestions should be mailed to: [email protected] */ #ifndef _3W_9XXX_H #define _3W_9XXX_H /* AEN string type */ twa_message_type; /* AEN strings */ static twa_message_type twa_aen_table[] = …; /* AEN severity table */ static char *twa_aen_severity_table[] = …; /* Error strings */ static twa_message_type twa_error_table[] = …; /* Control register bit definitions */ #define TW_CONTROL_CLEAR_HOST_INTERRUPT … #define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT … #define TW_CONTROL_MASK_COMMAND_INTERRUPT … #define TW_CONTROL_MASK_RESPONSE_INTERRUPT … #define TW_CONTROL_UNMASK_COMMAND_INTERRUPT … #define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT … #define TW_CONTROL_CLEAR_ERROR_STATUS … #define TW_CONTROL_ISSUE_SOFT_RESET … #define TW_CONTROL_ENABLE_INTERRUPTS … #define TW_CONTROL_DISABLE_INTERRUPTS … #define TW_CONTROL_ISSUE_HOST_INTERRUPT … #define TW_CONTROL_CLEAR_PARITY_ERROR … #define TW_CONTROL_CLEAR_QUEUE_ERROR … #define TW_CONTROL_CLEAR_PCI_ABORT … /* Status register bit definitions */ #define TW_STATUS_MAJOR_VERSION_MASK … #define TW_STATUS_MINOR_VERSION_MASK … #define TW_STATUS_PCI_PARITY_ERROR … #define TW_STATUS_QUEUE_ERROR … #define TW_STATUS_MICROCONTROLLER_ERROR … #define TW_STATUS_PCI_ABORT … #define TW_STATUS_HOST_INTERRUPT … #define TW_STATUS_ATTENTION_INTERRUPT … #define TW_STATUS_COMMAND_INTERRUPT … #define TW_STATUS_RESPONSE_INTERRUPT … #define TW_STATUS_COMMAND_QUEUE_FULL … #define TW_STATUS_RESPONSE_QUEUE_EMPTY … #define TW_STATUS_MICROCONTROLLER_READY … #define TW_STATUS_COMMAND_QUEUE_EMPTY … #define TW_STATUS_EXPECTED_BITS … #define TW_STATUS_UNEXPECTED_BITS … #define TW_STATUS_VALID_INTERRUPT … /* PCI related defines */ #define TW_PCI_CLEAR_PARITY_ERRORS … #define TW_PCI_CLEAR_PCI_ABORT … /* Command packet opcodes used by the driver */ #define TW_OP_INIT_CONNECTION … #define TW_OP_GET_PARAM … #define TW_OP_SET_PARAM … #define TW_OP_EXECUTE_SCSI … #define TW_OP_DOWNLOAD_FIRMWARE … #define TW_OP_RESET … /* Asynchronous Event Notification (AEN) codes used by the driver */ #define TW_AEN_QUEUE_EMPTY … #define TW_AEN_SOFT_RESET … #define TW_AEN_SYNC_TIME_WITH_HOST … #define TW_AEN_SEVERITY_ERROR … #define TW_AEN_SEVERITY_DEBUG … #define TW_AEN_NOT_RETRIEVED … #define TW_AEN_RETRIEVED … /* Command state defines */ #define TW_S_INITIAL … #define TW_S_STARTED … #define TW_S_POSTED … #define TW_S_PENDING … #define TW_S_COMPLETED … #define TW_S_FINISHED … /* Compatibility defines */ #define TW_9000_ARCH_ID … #define TW_CURRENT_DRIVER_SRL … #define TW_CURRENT_DRIVER_BUILD … #define TW_CURRENT_DRIVER_BRANCH … /* Misc defines */ #define TW_9550SX_DRAIN_COMPLETED … #define TW_SECTOR_SIZE … #define TW_ALIGNMENT_9000 … #define TW_ALIGNMENT_9000_SGL … #define TW_MAX_UNITS … #define TW_MAX_UNITS_9650SE … #define TW_INIT_MESSAGE_CREDITS … #define TW_INIT_COMMAND_PACKET_SIZE … #define TW_INIT_COMMAND_PACKET_SIZE_EXTENDED … #define TW_EXTENDED_INIT_CONNECT … #define TW_BUNDLED_FW_SAFE_TO_FLASH … #define TW_CTLR_FW_RECOMMENDS_FLASH … #define TW_CTLR_FW_COMPATIBLE … #define TW_BASE_FW_SRL … #define TW_BASE_FW_BRANCH … #define TW_BASE_FW_BUILD … #define TW_FW_SRL_LUNS_SUPPORTED … #define TW_Q_LENGTH … #define TW_Q_START … #define TW_MAX_SLOT … #define TW_MAX_RESET_TRIES … #define TW_MAX_CMDS_PER_LUN … #define TW_MAX_RESPONSE_DRAIN … #define TW_MAX_AEN_DRAIN … #define TW_IN_RESET … #define TW_USING_MSI … #define TW_IN_ATTENTION_LOOP … #define TW_MAX_SECTORS … #define TW_AEN_WAIT_TIME … #define TW_IOCTL_WAIT_TIME … #define TW_MAX_CDB_LEN … #define TW_ISR_DONT_COMPLETE … #define TW_ISR_DONT_RESULT … #define TW_IOCTL_CHRDEV_TIMEOUT … #define TW_IOCTL_CHRDEV_FREE … #define TW_COMMAND_OFFSET … #define TW_VERSION_TABLE … #define TW_TIMEKEEP_TABLE … #define TW_INFORMATION_TABLE … #define TW_PARAM_FWVER … #define TW_PARAM_FWVER_LENGTH … #define TW_PARAM_BIOSVER … #define TW_PARAM_BIOSVER_LENGTH … #define TW_PARAM_PORTCOUNT … #define TW_PARAM_PORTCOUNT_LENGTH … #define TW_MIN_SGL_LENGTH … #define TW_MAX_SENSE_LENGTH … #define TW_EVENT_SOURCE_AEN … #define TW_EVENT_SOURCE_COMMAND … #define TW_EVENT_SOURCE_PCHIP … #define TW_EVENT_SOURCE_DRIVER … #define TW_IOCTL_GET_COMPATIBILITY_INFO … #define TW_IOCTL_GET_LAST_EVENT … #define TW_IOCTL_GET_FIRST_EVENT … #define TW_IOCTL_GET_NEXT_EVENT … #define TW_IOCTL_GET_PREVIOUS_EVENT … #define TW_IOCTL_GET_LOCK … #define TW_IOCTL_RELEASE_LOCK … #define TW_IOCTL_FIRMWARE_PASS_THROUGH … #define TW_IOCTL_ERROR_STATUS_NOT_LOCKED … #define TW_IOCTL_ERROR_STATUS_LOCKED … #define TW_IOCTL_ERROR_STATUS_NO_MORE_EVENTS … #define TW_IOCTL_ERROR_STATUS_AEN_CLOBBER … #define TW_IOCTL_ERROR_OS_EFAULT … #define TW_IOCTL_ERROR_OS_EINTR … #define TW_IOCTL_ERROR_OS_EINVAL … #define TW_IOCTL_ERROR_OS_ENOMEM … #define TW_IOCTL_ERROR_OS_ERESTARTSYS … #define TW_IOCTL_ERROR_OS_EIO … #define TW_IOCTL_ERROR_OS_ENOTTY … #define TW_IOCTL_ERROR_OS_ENODEV … #define TW_ALLOCATION_LENGTH … #define TW_SENSE_DATA_LENGTH … #define TW_STATUS_CHECK_CONDITION … #define TW_ERROR_LOGICAL_UNIT_NOT_SUPPORTED … #define TW_ERROR_UNIT_OFFLINE … #define TW_MESSAGE_SOURCE_CONTROLLER_ERROR … #define TW_MESSAGE_SOURCE_CONTROLLER_EVENT … #define TW_MESSAGE_SOURCE_LINUX_DRIVER … #define TW_DRIVER … #define TW_MESSAGE_SOURCE_LINUX_OS … #define TW_OS … #ifndef PCI_DEVICE_ID_3WARE_9000 #define PCI_DEVICE_ID_3WARE_9000 … #endif #ifndef PCI_DEVICE_ID_3WARE_9550SX #define PCI_DEVICE_ID_3WARE_9550SX … #endif #ifndef PCI_DEVICE_ID_3WARE_9650SE #define PCI_DEVICE_ID_3WARE_9650SE … #endif #ifndef PCI_DEVICE_ID_3WARE_9690SA #define PCI_DEVICE_ID_3WARE_9690SA … #endif /* Bitmask macros to eliminate bitfields */ /* opcode: 5, reserved: 3 */ #define TW_OPRES_IN(x,y) … #define TW_OP_OUT(x) … /* opcode: 5, sgloffset: 3 */ #define TW_OPSGL_IN(x,y) … #define TW_SGL_OUT(x) … /* severity: 3, reserved: 5 */ #define TW_SEV_OUT(x) … /* reserved_1: 4, response_id: 8, reserved_2: 20 */ #define TW_RESID_OUT(x) … /* request_id: 12, lun: 4 */ #define TW_REQ_LUN_IN(lun, request_id) … #define TW_LUN_OUT(lun) … /* Macros */ #define TW_CONTROL_REG_ADDR(x) … #define TW_STATUS_REG_ADDR(x) … #define TW_COMMAND_QUEUE_REG_ADDR(x) … #define TW_COMMAND_QUEUE_REG_ADDR_LARGE(x) … #define TW_RESPONSE_QUEUE_REG_ADDR(x) … #define TW_RESPONSE_QUEUE_REG_ADDR_LARGE(x) … #define TW_CLEAR_ALL_INTERRUPTS(x) … #define TW_CLEAR_ATTENTION_INTERRUPT(x) … #define TW_CLEAR_HOST_INTERRUPT(x) … #define TW_DISABLE_INTERRUPTS(x) … #define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) … #define TW_MASK_COMMAND_INTERRUPT(x) … #define TW_UNMASK_COMMAND_INTERRUPT(x) … #define TW_SOFT_RESET(x) … #define TW_PRINTK(h,a,b,c) … #define TW_MAX_LUNS(srl) … #define TW_COMMAND_SIZE … #define TW_APACHE_MAX_SGL_LENGTH … #define TW_ESCALADE_MAX_SGL_LENGTH … #define TW_PADDING_LENGTH … #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) twa_addr_t; #define TW_CPU_TO_SGL(x) … #else typedef __le32 twa_addr_t; #define TW_CPU_TO_SGL … #endif /* Scatter Gather List Entry */ TW_SG_Entry; /* Command Packet */ TW_Command; /* Command Packet for 9000+ controllers */ TW_Command_Apache; /* New command packet header */ TW_Command_Apache_Header; /* This struct is a union of the 2 command packets */ TW_Command_Full; /* Initconnection structure */ TW_Initconnect; /* Event info structure */ TW_Event; TW_Ioctl_Driver_Command; TW_Ioctl_Buf_Apache; /* Lock structure for ioctl get/release lock */ TW_Lock; /* GetParam descriptor */ PTW_Param_Apache; /* Response queue */ TW_Response_Queue; /* Compatibility information structure */ TW_Compatibility_Info; TW_Device_Extension; #endif /* _3W_9XXX_H */
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