/* SPDX-License-Identifier: GPL-2.0 */ /* * Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers * * This driver supports the newer, SCSI-based firmware interface only. * * Copyright 2018 Hannes Reinecke, SUSE Linux GmbH <[email protected]> * * Based on the original DAC960 driver, which has * Copyright 1998-2001 by Leonard N. Zubkoff <[email protected]> * Portions Copyright 2002 by Mylex (An IBM Business Unit) */ #ifndef _MYRS_H #define _MYRS_H #define MYRS_MAILBOX_TIMEOUT … #define MYRS_DCMD_TAG … #define MYRS_MCMD_TAG … #define MYRS_LINE_BUFFER_SIZE … #define MYRS_PRIMARY_MONITOR_INTERVAL … #define MYRS_SECONDARY_MONITOR_INTERVAL … /* Maximum number of Scatter/Gather Segments supported */ #define MYRS_SG_LIMIT … /* * Number of Command and Status Mailboxes used by the * DAC960 V2 Firmware Memory Mailbox Interface. */ #define MYRS_MAX_CMD_MBOX … #define MYRS_MAX_STAT_MBOX … #define MYRS_DCDB_SIZE … #define MYRS_SENSE_SIZE … /* * DAC960 V2 Firmware Command Opcodes. */ enum myrs_cmd_opcode { … } __packed; /* * DAC960 V2 Firmware IOCTL Opcodes. */ enum myrs_ioctl_opcode { … } __packed; /* * DAC960 V2 Firmware Command Status Codes. */ #define MYRS_STATUS_SUCCESS … #define MYRS_STATUS_FAILED … #define MYRS_STATUS_DEVICE_BUSY … #define MYRS_STATUS_DEVICE_NON_RESPONSIVE … #define MYRS_STATUS_DEVICE_NON_RESPONSIVE2 … #define MYRS_STATUS_RESERVATION_CONFLICT … /* * DAC960 V2 Firmware Memory Type structure. */ struct myrs_mem_type { … }; /* * DAC960 V2 Firmware Processor Type structure. */ enum myrs_cpu_type { … } __packed; /* * DAC960 V2 Firmware Get Controller Info reply structure. */ struct myrs_ctlr_info { … }; /* * DAC960 V2 Firmware Device State type. */ enum myrs_devstate { … } __packed; /* * DAC960 V2 RAID Levels */ enum myrs_raid_level { … } __packed; enum myrs_stripe_size { … } __packed; enum myrs_cacheline_size { … } __packed; /* * DAC960 V2 Firmware Get Logical Device Info reply structure. */ struct myrs_ldev_info { … }; /* * DAC960 V2 Firmware Get Physical Device Info reply structure. */ struct myrs_pdev_info { … }; /* * DAC960 V2 Firmware Health Status Buffer structure. */ struct myrs_fwstat { … }; /* * DAC960 V2 Firmware Get Event reply structure. */ struct myrs_event { … }; /* * DAC960 V2 Firmware Command Control Bits structure. */ struct myrs_cmd_ctrl { … }; /* * DAC960 V2 Firmware Command Timeout structure. */ struct myrs_cmd_tmo { … }; /* * DAC960 V2 Firmware Physical Device structure. */ struct myrs_pdev { … } __packed; /* * DAC960 V2 Firmware Logical Device structure. */ struct myrs_ldev { … } __packed; /* * DAC960 V2 Firmware Operation Device type. */ enum myrs_opdev { … } __packed; /* * DAC960 V2 Firmware Translate Physical To Logical Device structure. */ struct myrs_devmap { … }; /* * DAC960 V2 Firmware Scatter/Gather List Entry structure. */ struct myrs_sge { … }; /* * DAC960 V2 Firmware Data Transfer Memory Address structure. */ myrs_sgl; /* * 64 Byte DAC960 V2 Firmware Command Mailbox structure. */ myrs_cmd_mbox; /* * DAC960 V2 Firmware Controller Status Mailbox structure. */ struct myrs_stat_mbox { … }; struct myrs_cmdblk { … }; /* * DAC960 Driver Controller structure. */ struct myrs_hba { … }; enable_mbox_t; myrs_hwinit_t; struct myrs_privdata { … }; /* * DAC960 GEM Series Controller Interface Register Offsets. */ #define DAC960_GEM_mmio_size … enum DAC960_GEM_reg_offset { … }; /* * DAC960 GEM Series Inbound Door Bell Register. */ #define DAC960_GEM_IDB_HWMBOX_NEW_CMD … #define DAC960_GEM_IDB_HWMBOX_ACK_STS … #define DAC960_GEM_IDB_GEN_IRQ … #define DAC960_GEM_IDB_CTRL_RESET … #define DAC960_GEM_IDB_MMBOX_NEW_CMD … #define DAC960_GEM_IDB_HWMBOX_FULL … #define DAC960_GEM_IDB_INIT_IN_PROGRESS … /* * DAC960 GEM Series Outbound Door Bell Register. */ #define DAC960_GEM_ODB_HWMBOX_ACK_IRQ … #define DAC960_GEM_ODB_MMBOX_ACK_IRQ … #define DAC960_GEM_ODB_HWMBOX_STS_AVAIL … #define DAC960_GEM_ODB_MMBOX_STS_AVAIL … /* * DAC960 GEM Series Interrupt Mask Register. */ #define DAC960_GEM_IRQMASK_HWMBOX_IRQ … #define DAC960_GEM_IRQMASK_MMBOX_IRQ … /* * DAC960 GEM Series Error Status Register. */ #define DAC960_GEM_ERRSTS_PENDING … /* * dma_addr_writeql is provided to write dma_addr_t types * to a 64-bit pci address space register. The controller * will accept having the register written as two 32-bit * values. * * In HIGHMEM kernels, dma_addr_t is a 64-bit value. * without HIGHMEM, dma_addr_t is a 32-bit value. * * The compiler should always fix up the assignment * to u.wq appropriately, depending upon the size of * dma_addr_t. */ static inline void dma_addr_writeql(dma_addr_t addr, void __iomem *write_address) { … } /* * DAC960 BA Series Controller Interface Register Offsets. */ #define DAC960_BA_mmio_size … enum DAC960_BA_reg_offset { … }; /* * DAC960 BA Series Inbound Door Bell Register. */ #define DAC960_BA_IDB_HWMBOX_NEW_CMD … #define DAC960_BA_IDB_HWMBOX_ACK_STS … #define DAC960_BA_IDB_GEN_IRQ … #define DAC960_BA_IDB_CTRL_RESET … #define DAC960_BA_IDB_MMBOX_NEW_CMD … #define DAC960_BA_IDB_HWMBOX_EMPTY … #define DAC960_BA_IDB_INIT_DONE … /* * DAC960 BA Series Outbound Door Bell Register. */ #define DAC960_BA_ODB_HWMBOX_ACK_IRQ … #define DAC960_BA_ODB_MMBOX_ACK_IRQ … #define DAC960_BA_ODB_HWMBOX_STS_AVAIL … #define DAC960_BA_ODB_MMBOX_STS_AVAIL … /* * DAC960 BA Series Interrupt Mask Register. */ #define DAC960_BA_IRQMASK_DISABLE_IRQ … #define DAC960_BA_IRQMASK_DISABLEW_I2O … /* * DAC960 BA Series Error Status Register. */ #define DAC960_BA_ERRSTS_PENDING … /* * DAC960 LP Series Controller Interface Register Offsets. */ #define DAC960_LP_mmio_size … enum DAC960_LP_reg_offset { … }; /* * DAC960 LP Series Inbound Door Bell Register. */ #define DAC960_LP_IDB_HWMBOX_NEW_CMD … #define DAC960_LP_IDB_HWMBOX_ACK_STS … #define DAC960_LP_IDB_GEN_IRQ … #define DAC960_LP_IDB_CTRL_RESET … #define DAC960_LP_IDB_MMBOX_NEW_CMD … #define DAC960_LP_IDB_HWMBOX_FULL … #define DAC960_LP_IDB_INIT_IN_PROGRESS … /* * DAC960 LP Series Outbound Door Bell Register. */ #define DAC960_LP_ODB_HWMBOX_ACK_IRQ … #define DAC960_LP_ODB_MMBOX_ACK_IRQ … #define DAC960_LP_ODB_HWMBOX_STS_AVAIL … #define DAC960_LP_ODB_MMBOX_STS_AVAIL … /* * DAC960 LP Series Interrupt Mask Register. */ #define DAC960_LP_IRQMASK_DISABLE_IRQ … /* * DAC960 LP Series Error Status Register. */ #define DAC960_LP_ERRSTS_PENDING … #endif /* _MYRS_H */
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