/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/ * Andrew F. Davis <[email protected]> * * Based on the TPS65218 driver and the previous TPS65912 driver by * Margarita Olaya Cabrera <[email protected]> */ #ifndef __LINUX_MFD_TPS65912_H #define __LINUX_MFD_TPS65912_H #include <linux/device.h> #include <linux/regmap.h> /* List of registers for TPS65912 */ #define TPS65912_DCDC1_CTRL … #define TPS65912_DCDC2_CTRL … #define TPS65912_DCDC3_CTRL … #define TPS65912_DCDC4_CTRL … #define TPS65912_DCDC1_OP … #define TPS65912_DCDC1_AVS … #define TPS65912_DCDC1_LIMIT … #define TPS65912_DCDC2_OP … #define TPS65912_DCDC2_AVS … #define TPS65912_DCDC2_LIMIT … #define TPS65912_DCDC3_OP … #define TPS65912_DCDC3_AVS … #define TPS65912_DCDC3_LIMIT … #define TPS65912_DCDC4_OP … #define TPS65912_DCDC4_AVS … #define TPS65912_DCDC4_LIMIT … #define TPS65912_LDO1_OP … #define TPS65912_LDO1_AVS … #define TPS65912_LDO1_LIMIT … #define TPS65912_LDO2_OP … #define TPS65912_LDO2_AVS … #define TPS65912_LDO2_LIMIT … #define TPS65912_LDO3_OP … #define TPS65912_LDO3_AVS … #define TPS65912_LDO3_LIMIT … #define TPS65912_LDO4_OP … #define TPS65912_LDO4_AVS … #define TPS65912_LDO4_LIMIT … #define TPS65912_LDO5 … #define TPS65912_LDO6 … #define TPS65912_LDO7 … #define TPS65912_LDO8 … #define TPS65912_LDO9 … #define TPS65912_LDO10 … #define TPS65912_THRM … #define TPS65912_CLK32OUT … #define TPS65912_DEVCTRL … #define TPS65912_DEVCTRL2 … #define TPS65912_I2C_SPI_CFG … #define TPS65912_KEEP_ON … #define TPS65912_KEEP_ON2 … #define TPS65912_SET_OFF1 … #define TPS65912_SET_OFF2 … #define TPS65912_DEF_VOLT … #define TPS65912_DEF_VOLT_MAPPING … #define TPS65912_DISCHARGE … #define TPS65912_DISCHARGE2 … #define TPS65912_EN1_SET1 … #define TPS65912_EN1_SET2 … #define TPS65912_EN2_SET1 … #define TPS65912_EN2_SET2 … #define TPS65912_EN3_SET1 … #define TPS65912_EN3_SET2 … #define TPS65912_EN4_SET1 … #define TPS65912_EN4_SET2 … #define TPS65912_PGOOD … #define TPS65912_PGOOD2 … #define TPS65912_INT_STS … #define TPS65912_INT_MSK … #define TPS65912_INT_STS2 … #define TPS65912_INT_MSK2 … #define TPS65912_INT_STS3 … #define TPS65912_INT_MSK3 … #define TPS65912_INT_STS4 … #define TPS65912_INT_MSK4 … #define TPS65912_GPIO1 … #define TPS65912_GPIO2 … #define TPS65912_GPIO3 … #define TPS65912_GPIO4 … #define TPS65912_GPIO5 … #define TPS65912_VMON … #define TPS65912_LEDA_CTRL1 … #define TPS65912_LEDA_CTRL2 … #define TPS65912_LEDA_CTRL3 … #define TPS65912_LEDA_CTRL4 … #define TPS65912_LEDA_CTRL5 … #define TPS65912_LEDA_CTRL6 … #define TPS65912_LEDA_CTRL7 … #define TPS65912_LEDA_CTRL8 … #define TPS65912_LEDB_CTRL1 … #define TPS65912_LEDB_CTRL2 … #define TPS65912_LEDB_CTRL3 … #define TPS65912_LEDB_CTRL4 … #define TPS65912_LEDB_CTRL5 … #define TPS65912_LEDB_CTRL6 … #define TPS65912_LEDB_CTRL7 … #define TPS65912_LEDB_CTRL8 … #define TPS65912_LEDC_CTRL1 … #define TPS65912_LEDC_CTRL2 … #define TPS65912_LEDC_CTRL3 … #define TPS65912_LEDC_CTRL4 … #define TPS65912_LEDC_CTRL5 … #define TPS65912_LEDC_CTRL6 … #define TPS65912_LEDC_CTRL7 … #define TPS65912_LEDC_CTRL8 … #define TPS65912_LED_RAMP_UP_TIME … #define TPS65912_LED_RAMP_DOWN_TIME … #define TPS65912_LED_SEQ_EN … #define TPS65912_LOADSWITCH … #define TPS65912_SPARE … #define TPS65912_VERNUM … #define TPS6591X_MAX_REGISTER … /* INT_STS Register field definitions */ #define TPS65912_INT_STS_PWRHOLD_F … #define TPS65912_INT_STS_VMON … #define TPS65912_INT_STS_PWRON … #define TPS65912_INT_STS_PWRON_LP … #define TPS65912_INT_STS_PWRHOLD_R … #define TPS65912_INT_STS_HOTDIE … #define TPS65912_INT_STS_GPIO1_R … #define TPS65912_INT_STS_GPIO1_F … /* INT_STS Register field definitions */ #define TPS65912_INT_STS2_GPIO2_R … #define TPS65912_INT_STS2_GPIO2_F … #define TPS65912_INT_STS2_GPIO3_R … #define TPS65912_INT_STS2_GPIO3_F … #define TPS65912_INT_STS2_GPIO4_R … #define TPS65912_INT_STS2_GPIO4_F … #define TPS65912_INT_STS2_GPIO5_R … #define TPS65912_INT_STS2_GPIO5_F … /* INT_STS Register field definitions */ #define TPS65912_INT_STS3_PGOOD_DCDC1 … #define TPS65912_INT_STS3_PGOOD_DCDC2 … #define TPS65912_INT_STS3_PGOOD_DCDC3 … #define TPS65912_INT_STS3_PGOOD_DCDC4 … #define TPS65912_INT_STS3_PGOOD_LDO1 … #define TPS65912_INT_STS3_PGOOD_LDO2 … #define TPS65912_INT_STS3_PGOOD_LDO3 … #define TPS65912_INT_STS3_PGOOD_LDO4 … /* INT_STS Register field definitions */ #define TPS65912_INT_STS4_PGOOD_LDO5 … #define TPS65912_INT_STS4_PGOOD_LDO6 … #define TPS65912_INT_STS4_PGOOD_LDO7 … #define TPS65912_INT_STS4_PGOOD_LDO8 … #define TPS65912_INT_STS4_PGOOD_LDO9 … #define TPS65912_INT_STS4_PGOOD_LDO10 … /* GPIO 1 and 2 Register field definitions */ #define GPIO_SLEEP_MASK … #define GPIO_SLEEP_SHIFT … #define GPIO_DEB_MASK … #define GPIO_DEB_SHIFT … #define GPIO_CFG_MASK … #define GPIO_CFG_SHIFT … #define GPIO_STS_MASK … #define GPIO_STS_SHIFT … #define GPIO_SET_MASK … #define GPIO_SET_SHIFT … /* GPIO 3 Register field definitions */ #define GPIO3_SLEEP_MASK … #define GPIO3_SLEEP_SHIFT … #define GPIO3_SEL_MASK … #define GPIO3_SEL_SHIFT … #define GPIO3_ODEN_MASK … #define GPIO3_ODEN_SHIFT … #define GPIO3_DEB_MASK … #define GPIO3_DEB_SHIFT … #define GPIO3_PDEN_MASK … #define GPIO3_PDEN_SHIFT … #define GPIO3_CFG_MASK … #define GPIO3_CFG_SHIFT … #define GPIO3_STS_MASK … #define GPIO3_STS_SHIFT … #define GPIO3_SET_MASK … #define GPIO3_SET_SHIFT … /* GPIO 4 Register field definitions */ #define GPIO4_SLEEP_MASK … #define GPIO4_SLEEP_SHIFT … #define GPIO4_SEL_MASK … #define GPIO4_SEL_SHIFT … #define GPIO4_ODEN_MASK … #define GPIO4_ODEN_SHIFT … #define GPIO4_DEB_MASK … #define GPIO4_DEB_SHIFT … #define GPIO4_PDEN_MASK … #define GPIO4_PDEN_SHIFT … #define GPIO4_CFG_MASK … #define GPIO4_CFG_SHIFT … #define GPIO4_STS_MASK … #define GPIO4_STS_SHIFT … #define GPIO4_SET_MASK … #define GPIO4_SET_SHIFT … /* Register THERM (0x80) register.RegisterDescription */ #define THERM_THERM_HD_MASK … #define THERM_THERM_HD_SHIFT … #define THERM_THERM_TS_MASK … #define THERM_THERM_TS_SHIFT … #define THERM_THERM_HDSEL_MASK … #define THERM_THERM_HDSEL_SHIFT … #define THERM_RSVD1_MASK … #define THERM_RSVD1_SHIFT … #define THERM_THERM_STATE_MASK … #define THERM_THERM_STATE_SHIFT … /* Register DCDCCTRL1 register.RegisterDescription */ #define DCDCCTRL_VCON_ENABLE_MASK … #define DCDCCTRL_VCON_ENABLE_SHIFT … #define DCDCCTRL_VCON_RANGE1_MASK … #define DCDCCTRL_VCON_RANGE1_SHIFT … #define DCDCCTRL_VCON_RANGE0_MASK … #define DCDCCTRL_VCON_RANGE0_SHIFT … #define DCDCCTRL_TSTEP2_MASK … #define DCDCCTRL_TSTEP2_SHIFT … #define DCDCCTRL_TSTEP1_MASK … #define DCDCCTRL_TSTEP1_SHIFT … #define DCDCCTRL_TSTEP0_MASK … #define DCDCCTRL_TSTEP0_SHIFT … #define DCDCCTRL_DCDC1_MODE_MASK … #define DCDCCTRL_DCDC1_MODE_SHIFT … /* Register DCDCCTRL2 and DCDCCTRL3 register.RegisterDescription */ #define DCDCCTRL_TSTEP2_MASK … #define DCDCCTRL_TSTEP2_SHIFT … #define DCDCCTRL_TSTEP1_MASK … #define DCDCCTRL_TSTEP1_SHIFT … #define DCDCCTRL_TSTEP0_MASK … #define DCDCCTRL_TSTEP0_SHIFT … #define DCDCCTRL_DCDC_MODE_MASK … #define DCDCCTRL_DCDC_MODE_SHIFT … #define DCDCCTRL_RSVD0_MASK … #define DCDCCTRL_RSVD0_SHIFT … /* Register DCDCCTRL4 register.RegisterDescription */ #define DCDCCTRL_RAMP_TIME_MASK … #define DCDCCTRL_RAMP_TIME_SHIFT … /* Register DCDCx_AVS */ #define DCDC_AVS_ENABLE_MASK … #define DCDC_AVS_ENABLE_SHIFT … #define DCDC_AVS_ECO_MASK … #define DCDC_AVS_ECO_SHIFT … /* Register DCDCx_LIMIT */ #define DCDC_LIMIT_RANGE_MASK … #define DCDC_LIMIT_RANGE_SHIFT … #define DCDC_LIMIT_MAX_SEL_MASK … #define DCDC_LIMIT_MAX_SEL_SHIFT … /* Define the TPS65912 IRQ numbers */ enum tps65912_irqs { … }; /* * struct tps65912 - state holder for the tps65912 driver * * Device data may be used to access the TPS65912 chip */ struct tps65912 { … }; extern const struct regmap_config tps65912_regmap_config; int tps65912_device_init(struct tps65912 *tps); #endif /* __LINUX_MFD_TPS65912_H */
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