/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * tps65910.h -- TI TPS6591x * * Copyright 2010-2011 Texas Instruments Inc. * * Author: Graeme Gregory <[email protected]> * Author: Jorge Eduardo Candelaria <[email protected]> * Author: Arnaud Deconinck <[email protected]> */ #ifndef __LINUX_MFD_TPS65910_H #define __LINUX_MFD_TPS65910_H #include <linux/gpio.h> #include <linux/regmap.h> /* TPS chip id list */ #define TPS65910 … #define TPS65911 … /* TPS regulator type list */ #define REGULATOR_LDO … #define REGULATOR_DCDC … /* * List of registers for component TPS65910 * */ #define TPS65910_SECONDS … #define TPS65910_MINUTES … #define TPS65910_HOURS … #define TPS65910_DAYS … #define TPS65910_MONTHS … #define TPS65910_YEARS … #define TPS65910_WEEKS … #define TPS65910_ALARM_SECONDS … #define TPS65910_ALARM_MINUTES … #define TPS65910_ALARM_HOURS … #define TPS65910_ALARM_DAYS … #define TPS65910_ALARM_MONTHS … #define TPS65910_ALARM_YEARS … #define TPS65910_RTC_CTRL … #define TPS65910_RTC_STATUS … #define TPS65910_RTC_INTERRUPTS … #define TPS65910_RTC_COMP_LSB … #define TPS65910_RTC_COMP_MSB … #define TPS65910_RTC_RES_PROG … #define TPS65910_RTC_RESET_STATUS … #define TPS65910_BCK1 … #define TPS65910_BCK2 … #define TPS65910_BCK3 … #define TPS65910_BCK4 … #define TPS65910_BCK5 … #define TPS65910_PUADEN … #define TPS65910_REF … #define TPS65910_VRTC … #define TPS65910_VIO … #define TPS65910_VDD1 … #define TPS65910_VDD1_OP … #define TPS65910_VDD1_SR … #define TPS65910_VDD2 … #define TPS65910_VDD2_OP … #define TPS65910_VDD2_SR … #define TPS65910_VDD3 … #define TPS65910_VDIG1 … #define TPS65910_VDIG2 … #define TPS65910_VAUX1 … #define TPS65910_VAUX2 … #define TPS65910_VAUX33 … #define TPS65910_VMMC … #define TPS65910_VPLL … #define TPS65910_VDAC … #define TPS65910_THERM … #define TPS65910_BBCH … #define TPS65910_DCDCCTRL … #define TPS65910_DEVCTRL … #define TPS65910_DEVCTRL2 … #define TPS65910_SLEEP_KEEP_LDO_ON … #define TPS65910_SLEEP_KEEP_RES_ON … #define TPS65910_SLEEP_SET_LDO_OFF … #define TPS65910_SLEEP_SET_RES_OFF … #define TPS65910_EN1_LDO_ASS … #define TPS65910_EN1_SMPS_ASS … #define TPS65910_EN2_LDO_ASS … #define TPS65910_EN2_SMPS_ASS … #define TPS65910_EN3_LDO_ASS … #define TPS65910_SPARE … #define TPS65910_INT_STS … #define TPS65910_INT_MSK … #define TPS65910_INT_STS2 … #define TPS65910_INT_MSK2 … #define TPS65910_INT_STS3 … #define TPS65910_INT_MSK3 … #define TPS65910_GPIO0 … #define TPS65910_GPIO1 … #define TPS65910_GPIO2 … #define TPS65910_GPIO3 … #define TPS65910_GPIO4 … #define TPS65910_GPIO5 … #define TPS65910_GPIO6 … #define TPS65910_GPIO7 … #define TPS65910_GPIO8 … #define TPS65910_JTAGVERNUM … #define TPS65910_MAX_REGISTER … /* * List of registers specific to TPS65911 */ #define TPS65911_VDDCTRL … #define TPS65911_VDDCTRL_OP … #define TPS65911_VDDCTRL_SR … #define TPS65911_LDO1 … #define TPS65911_LDO2 … #define TPS65911_LDO5 … #define TPS65911_LDO8 … #define TPS65911_LDO7 … #define TPS65911_LDO6 … #define TPS65911_LDO4 … #define TPS65911_LDO3 … #define TPS65911_VMBCH … #define TPS65911_VMBCH2 … /* * List of register bitfields for component TPS65910 * */ /* RTC_CTRL_REG bitfields */ #define TPS65910_RTC_CTRL_STOP_RTC … #define TPS65910_RTC_CTRL_AUTO_COMP … #define TPS65910_RTC_CTRL_GET_TIME … /* RTC_STATUS_REG bitfields */ #define TPS65910_RTC_STATUS_ALARM … /* RTC_INTERRUPTS_REG bitfields */ #define TPS65910_RTC_INTERRUPTS_EVERY … #define TPS65910_RTC_INTERRUPTS_IT_ALARM … /*Register BCK1 (0x80) register.RegisterDescription */ #define BCK1_BCKUP_MASK … #define BCK1_BCKUP_SHIFT … /*Register BCK2 (0x80) register.RegisterDescription */ #define BCK2_BCKUP_MASK … #define BCK2_BCKUP_SHIFT … /*Register BCK3 (0x80) register.RegisterDescription */ #define BCK3_BCKUP_MASK … #define BCK3_BCKUP_SHIFT … /*Register BCK4 (0x80) register.RegisterDescription */ #define BCK4_BCKUP_MASK … #define BCK4_BCKUP_SHIFT … /*Register BCK5 (0x80) register.RegisterDescription */ #define BCK5_BCKUP_MASK … #define BCK5_BCKUP_SHIFT … /*Register PUADEN (0x80) register.RegisterDescription */ #define PUADEN_EN3P_MASK … #define PUADEN_EN3P_SHIFT … #define PUADEN_I2CCTLP_MASK … #define PUADEN_I2CCTLP_SHIFT … #define PUADEN_I2CSRP_MASK … #define PUADEN_I2CSRP_SHIFT … #define PUADEN_PWRONP_MASK … #define PUADEN_PWRONP_SHIFT … #define PUADEN_SLEEPP_MASK … #define PUADEN_SLEEPP_SHIFT … #define PUADEN_PWRHOLDP_MASK … #define PUADEN_PWRHOLDP_SHIFT … #define PUADEN_BOOT1P_MASK … #define PUADEN_BOOT1P_SHIFT … #define PUADEN_BOOT0P_MASK … #define PUADEN_BOOT0P_SHIFT … /*Register REF (0x80) register.RegisterDescription */ #define REF_VMBCH_SEL_MASK … #define REF_VMBCH_SEL_SHIFT … #define REF_ST_MASK … #define REF_ST_SHIFT … /*Register VRTC (0x80) register.RegisterDescription */ #define VRTC_VRTC_OFFMASK_MASK … #define VRTC_VRTC_OFFMASK_SHIFT … #define VRTC_ST_MASK … #define VRTC_ST_SHIFT … /*Register VIO (0x80) register.RegisterDescription */ #define VIO_ILMAX_MASK … #define VIO_ILMAX_SHIFT … #define VIO_SEL_MASK … #define VIO_SEL_SHIFT … #define VIO_ST_MASK … #define VIO_ST_SHIFT … /*Register VDD1 (0x80) register.RegisterDescription */ #define VDD1_VGAIN_SEL_MASK … #define VDD1_VGAIN_SEL_SHIFT … #define VDD1_ILMAX_MASK … #define VDD1_ILMAX_SHIFT … #define VDD1_TSTEP_MASK … #define VDD1_TSTEP_SHIFT … #define VDD1_ST_MASK … #define VDD1_ST_SHIFT … /*Register VDD1_OP (0x80) register.RegisterDescription */ #define VDD1_OP_CMD_MASK … #define VDD1_OP_CMD_SHIFT … #define VDD1_OP_SEL_MASK … #define VDD1_OP_SEL_SHIFT … /*Register VDD1_SR (0x80) register.RegisterDescription */ #define VDD1_SR_SEL_MASK … #define VDD1_SR_SEL_SHIFT … /*Register VDD2 (0x80) register.RegisterDescription */ #define VDD2_VGAIN_SEL_MASK … #define VDD2_VGAIN_SEL_SHIFT … #define VDD2_ILMAX_MASK … #define VDD2_ILMAX_SHIFT … #define VDD2_TSTEP_MASK … #define VDD2_TSTEP_SHIFT … #define VDD2_ST_MASK … #define VDD2_ST_SHIFT … /*Register VDD2_OP (0x80) register.RegisterDescription */ #define VDD2_OP_CMD_MASK … #define VDD2_OP_CMD_SHIFT … #define VDD2_OP_SEL_MASK … #define VDD2_OP_SEL_SHIFT … /*Register VDD2_SR (0x80) register.RegisterDescription */ #define VDD2_SR_SEL_MASK … #define VDD2_SR_SEL_SHIFT … /*Registers VDD1, VDD2 voltage values definitions */ #define VDD1_2_NUM_VOLT_FINE … #define VDD1_2_NUM_VOLT_COARSE … #define VDD1_2_MIN_VOLT … #define VDD1_2_OFFSET … /*Register VDD3 (0x80) register.RegisterDescription */ #define VDD3_CKINEN_MASK … #define VDD3_CKINEN_SHIFT … #define VDD3_ST_MASK … #define VDD3_ST_SHIFT … #define VDDCTRL_MIN_VOLT … #define VDDCTRL_OFFSET … /*Registers VDIG (0x80) to VDAC register.RegisterDescription */ #define LDO_SEL_MASK … #define LDO_SEL_SHIFT … #define LDO_ST_MASK … #define LDO_ST_SHIFT … #define LDO_ST_ON_BIT … #define LDO_ST_MODE_BIT … /* Registers LDO1 to LDO8 in tps65910 */ #define LDO1_SEL_MASK … #define LDO3_SEL_MASK … #define LDO_MIN_VOLT … #define LDO_MAX_VOLT … /*Register VDIG1 (0x80) register.RegisterDescription */ #define VDIG1_SEL_MASK … #define VDIG1_SEL_SHIFT … #define VDIG1_ST_MASK … #define VDIG1_ST_SHIFT … /*Register VDIG2 (0x80) register.RegisterDescription */ #define VDIG2_SEL_MASK … #define VDIG2_SEL_SHIFT … #define VDIG2_ST_MASK … #define VDIG2_ST_SHIFT … /*Register VAUX1 (0x80) register.RegisterDescription */ #define VAUX1_SEL_MASK … #define VAUX1_SEL_SHIFT … #define VAUX1_ST_MASK … #define VAUX1_ST_SHIFT … /*Register VAUX2 (0x80) register.RegisterDescription */ #define VAUX2_SEL_MASK … #define VAUX2_SEL_SHIFT … #define VAUX2_ST_MASK … #define VAUX2_ST_SHIFT … /*Register VAUX33 (0x80) register.RegisterDescription */ #define VAUX33_SEL_MASK … #define VAUX33_SEL_SHIFT … #define VAUX33_ST_MASK … #define VAUX33_ST_SHIFT … /*Register VMMC (0x80) register.RegisterDescription */ #define VMMC_SEL_MASK … #define VMMC_SEL_SHIFT … #define VMMC_ST_MASK … #define VMMC_ST_SHIFT … /*Register VPLL (0x80) register.RegisterDescription */ #define VPLL_SEL_MASK … #define VPLL_SEL_SHIFT … #define VPLL_ST_MASK … #define VPLL_ST_SHIFT … /*Register VDAC (0x80) register.RegisterDescription */ #define VDAC_SEL_MASK … #define VDAC_SEL_SHIFT … #define VDAC_ST_MASK … #define VDAC_ST_SHIFT … /*Register THERM (0x80) register.RegisterDescription */ #define THERM_THERM_HD_MASK … #define THERM_THERM_HD_SHIFT … #define THERM_THERM_TS_MASK … #define THERM_THERM_TS_SHIFT … #define THERM_THERM_HDSEL_MASK … #define THERM_THERM_HDSEL_SHIFT … #define THERM_RSVD1_MASK … #define THERM_RSVD1_SHIFT … #define THERM_THERM_STATE_MASK … #define THERM_THERM_STATE_SHIFT … /*Register BBCH (0x80) register.RegisterDescription */ #define BBCH_BBSEL_MASK … #define BBCH_BBSEL_SHIFT … /*Register DCDCCTRL (0x80) register.RegisterDescription */ #define DCDCCTRL_VDD2_PSKIP_MASK … #define DCDCCTRL_VDD2_PSKIP_SHIFT … #define DCDCCTRL_VDD1_PSKIP_MASK … #define DCDCCTRL_VDD1_PSKIP_SHIFT … #define DCDCCTRL_VIO_PSKIP_MASK … #define DCDCCTRL_VIO_PSKIP_SHIFT … #define DCDCCTRL_DCDCCKEXT_MASK … #define DCDCCTRL_DCDCCKEXT_SHIFT … #define DCDCCTRL_DCDCCKSYNC_MASK … #define DCDCCTRL_DCDCCKSYNC_SHIFT … /*Register DEVCTRL (0x80) register.RegisterDescription */ #define DEVCTRL_PWR_OFF_MASK … #define DEVCTRL_PWR_OFF_SHIFT … #define DEVCTRL_RTC_PWDN_MASK … #define DEVCTRL_RTC_PWDN_SHIFT … #define DEVCTRL_CK32K_CTRL_MASK … #define DEVCTRL_CK32K_CTRL_SHIFT … #define DEVCTRL_SR_CTL_I2C_SEL_MASK … #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT … #define DEVCTRL_DEV_OFF_RST_MASK … #define DEVCTRL_DEV_OFF_RST_SHIFT … #define DEVCTRL_DEV_ON_MASK … #define DEVCTRL_DEV_ON_SHIFT … #define DEVCTRL_DEV_SLP_MASK … #define DEVCTRL_DEV_SLP_SHIFT … #define DEVCTRL_DEV_OFF_MASK … #define DEVCTRL_DEV_OFF_SHIFT … /*Register DEVCTRL2 (0x80) register.RegisterDescription */ #define DEVCTRL2_TSLOT_LENGTH_MASK … #define DEVCTRL2_TSLOT_LENGTH_SHIFT … #define DEVCTRL2_SLEEPSIG_POL_MASK … #define DEVCTRL2_SLEEPSIG_POL_SHIFT … #define DEVCTRL2_PWON_LP_OFF_MASK … #define DEVCTRL2_PWON_LP_OFF_SHIFT … #define DEVCTRL2_PWON_LP_RST_MASK … #define DEVCTRL2_PWON_LP_RST_SHIFT … #define DEVCTRL2_IT_POL_MASK … #define DEVCTRL2_IT_POL_SHIFT … /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */ #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK … #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT … #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK … #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT … #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK … #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT … #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK … #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT … #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK … #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT … #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK … #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT … #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK … #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT … #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK … #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT … /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */ #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK … #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT … #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK … #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT … #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK … #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT … #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK … #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT … #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK … #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT … #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK … #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT … #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK … #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT … #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK … #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT … /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */ #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK … #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT … #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK … #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT … #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK … #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT … #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK … #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT … #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK … #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT … #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK … #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT … #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK … #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT … #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK … #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT … /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */ #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK … #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT … #define SLEEP_SET_RES_OFF_RSVD_MASK … #define SLEEP_SET_RES_OFF_RSVD_SHIFT … #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK … #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT … #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK … #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT … #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK … #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT … #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK … #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT … #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK … #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT … /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */ #define EN1_LDO_ASS_VDAC_EN1_MASK … #define EN1_LDO_ASS_VDAC_EN1_SHIFT … #define EN1_LDO_ASS_VPLL_EN1_MASK … #define EN1_LDO_ASS_VPLL_EN1_SHIFT … #define EN1_LDO_ASS_VAUX33_EN1_MASK … #define EN1_LDO_ASS_VAUX33_EN1_SHIFT … #define EN1_LDO_ASS_VAUX2_EN1_MASK … #define EN1_LDO_ASS_VAUX2_EN1_SHIFT … #define EN1_LDO_ASS_VAUX1_EN1_MASK … #define EN1_LDO_ASS_VAUX1_EN1_SHIFT … #define EN1_LDO_ASS_VDIG2_EN1_MASK … #define EN1_LDO_ASS_VDIG2_EN1_SHIFT … #define EN1_LDO_ASS_VDIG1_EN1_MASK … #define EN1_LDO_ASS_VDIG1_EN1_SHIFT … #define EN1_LDO_ASS_VMMC_EN1_MASK … #define EN1_LDO_ASS_VMMC_EN1_SHIFT … /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */ #define EN1_SMPS_ASS_RSVD_MASK … #define EN1_SMPS_ASS_RSVD_SHIFT … #define EN1_SMPS_ASS_SPARE_EN1_MASK … #define EN1_SMPS_ASS_SPARE_EN1_SHIFT … #define EN1_SMPS_ASS_VDD3_EN1_MASK … #define EN1_SMPS_ASS_VDD3_EN1_SHIFT … #define EN1_SMPS_ASS_VDD2_EN1_MASK … #define EN1_SMPS_ASS_VDD2_EN1_SHIFT … #define EN1_SMPS_ASS_VDD1_EN1_MASK … #define EN1_SMPS_ASS_VDD1_EN1_SHIFT … #define EN1_SMPS_ASS_VIO_EN1_MASK … #define EN1_SMPS_ASS_VIO_EN1_SHIFT … /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */ #define EN2_LDO_ASS_VDAC_EN2_MASK … #define EN2_LDO_ASS_VDAC_EN2_SHIFT … #define EN2_LDO_ASS_VPLL_EN2_MASK … #define EN2_LDO_ASS_VPLL_EN2_SHIFT … #define EN2_LDO_ASS_VAUX33_EN2_MASK … #define EN2_LDO_ASS_VAUX33_EN2_SHIFT … #define EN2_LDO_ASS_VAUX2_EN2_MASK … #define EN2_LDO_ASS_VAUX2_EN2_SHIFT … #define EN2_LDO_ASS_VAUX1_EN2_MASK … #define EN2_LDO_ASS_VAUX1_EN2_SHIFT … #define EN2_LDO_ASS_VDIG2_EN2_MASK … #define EN2_LDO_ASS_VDIG2_EN2_SHIFT … #define EN2_LDO_ASS_VDIG1_EN2_MASK … #define EN2_LDO_ASS_VDIG1_EN2_SHIFT … #define EN2_LDO_ASS_VMMC_EN2_MASK … #define EN2_LDO_ASS_VMMC_EN2_SHIFT … /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */ #define EN2_SMPS_ASS_RSVD_MASK … #define EN2_SMPS_ASS_RSVD_SHIFT … #define EN2_SMPS_ASS_SPARE_EN2_MASK … #define EN2_SMPS_ASS_SPARE_EN2_SHIFT … #define EN2_SMPS_ASS_VDD3_EN2_MASK … #define EN2_SMPS_ASS_VDD3_EN2_SHIFT … #define EN2_SMPS_ASS_VDD2_EN2_MASK … #define EN2_SMPS_ASS_VDD2_EN2_SHIFT … #define EN2_SMPS_ASS_VDD1_EN2_MASK … #define EN2_SMPS_ASS_VDD1_EN2_SHIFT … #define EN2_SMPS_ASS_VIO_EN2_MASK … #define EN2_SMPS_ASS_VIO_EN2_SHIFT … /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */ #define EN3_LDO_ASS_VDAC_EN3_MASK … #define EN3_LDO_ASS_VDAC_EN3_SHIFT … #define EN3_LDO_ASS_VPLL_EN3_MASK … #define EN3_LDO_ASS_VPLL_EN3_SHIFT … #define EN3_LDO_ASS_VAUX33_EN3_MASK … #define EN3_LDO_ASS_VAUX33_EN3_SHIFT … #define EN3_LDO_ASS_VAUX2_EN3_MASK … #define EN3_LDO_ASS_VAUX2_EN3_SHIFT … #define EN3_LDO_ASS_VAUX1_EN3_MASK … #define EN3_LDO_ASS_VAUX1_EN3_SHIFT … #define EN3_LDO_ASS_VDIG2_EN3_MASK … #define EN3_LDO_ASS_VDIG2_EN3_SHIFT … #define EN3_LDO_ASS_VDIG1_EN3_MASK … #define EN3_LDO_ASS_VDIG1_EN3_SHIFT … #define EN3_LDO_ASS_VMMC_EN3_MASK … #define EN3_LDO_ASS_VMMC_EN3_SHIFT … /*Register SPARE (0x80) register.RegisterDescription */ #define SPARE_SPARE_MASK … #define SPARE_SPARE_SHIFT … #define TPS65910_INT_STS_RTC_PERIOD_IT_MASK … #define TPS65910_INT_STS_RTC_PERIOD_IT_SHIFT … #define TPS65910_INT_STS_RTC_ALARM_IT_MASK … #define TPS65910_INT_STS_RTC_ALARM_IT_SHIFT … #define TPS65910_INT_STS_HOTDIE_IT_MASK … #define TPS65910_INT_STS_HOTDIE_IT_SHIFT … #define TPS65910_INT_STS_PWRHOLD_F_IT_MASK … #define TPS65910_INT_STS_PWRHOLD_F_IT_SHIFT … #define TPS65910_INT_STS_PWRON_LP_IT_MASK … #define TPS65910_INT_STS_PWRON_LP_IT_SHIFT … #define TPS65910_INT_STS_PWRON_IT_MASK … #define TPS65910_INT_STS_PWRON_IT_SHIFT … #define TPS65910_INT_STS_VMBHI_IT_MASK … #define TPS65910_INT_STS_VMBHI_IT_SHIFT … #define TPS65910_INT_STS_VMBDCH_IT_MASK … #define TPS65910_INT_STS_VMBDCH_IT_SHIFT … #define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK … #define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_SHIFT … #define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK … #define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_SHIFT … #define TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK … #define TPS65910_INT_MSK_HOTDIE_IT_MSK_SHIFT … #define TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK … #define TPS65910_INT_MSK_PWRHOLD_IT_MSK_SHIFT … #define TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK … #define TPS65910_INT_MSK_PWRON_LP_IT_MSK_SHIFT … #define TPS65910_INT_MSK_PWRON_IT_MSK_MASK … #define TPS65910_INT_MSK_PWRON_IT_MSK_SHIFT … #define TPS65910_INT_MSK_VMBHI_IT_MSK_MASK … #define TPS65910_INT_MSK_VMBHI_IT_MSK_SHIFT … #define TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK … #define TPS65910_INT_MSK_VMBDCH_IT_MSK_SHIFT … #define TPS65910_INT_STS2_GPIO0_F_IT_SHIFT … #define TPS65910_INT_STS2_GPIO0_F_IT_MASK … #define TPS65910_INT_STS2_GPIO0_R_IT_SHIFT … #define TPS65910_INT_STS2_GPIO0_R_IT_MASK … #define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_SHIFT … #define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK … #define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_SHIFT … #define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK … /*Register INT_STS (0x80) register.RegisterDescription */ #define INT_STS_RTC_PERIOD_IT_MASK … #define INT_STS_RTC_PERIOD_IT_SHIFT … #define INT_STS_RTC_ALARM_IT_MASK … #define INT_STS_RTC_ALARM_IT_SHIFT … #define INT_STS_HOTDIE_IT_MASK … #define INT_STS_HOTDIE_IT_SHIFT … #define INT_STS_PWRHOLD_R_IT_MASK … #define INT_STS_PWRHOLD_R_IT_SHIFT … #define INT_STS_PWRON_LP_IT_MASK … #define INT_STS_PWRON_LP_IT_SHIFT … #define INT_STS_PWRON_IT_MASK … #define INT_STS_PWRON_IT_SHIFT … #define INT_STS_VMBHI_IT_MASK … #define INT_STS_VMBHI_IT_SHIFT … #define INT_STS_PWRHOLD_F_IT_MASK … #define INT_STS_PWRHOLD_F_IT_SHIFT … /*Register INT_MSK (0x80) register.RegisterDescription */ #define INT_MSK_RTC_PERIOD_IT_MSK_MASK … #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT … #define INT_MSK_RTC_ALARM_IT_MSK_MASK … #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT … #define INT_MSK_HOTDIE_IT_MSK_MASK … #define INT_MSK_HOTDIE_IT_MSK_SHIFT … #define INT_MSK_PWRHOLD_R_IT_MSK_MASK … #define INT_MSK_PWRHOLD_R_IT_MSK_SHIFT … #define INT_MSK_PWRON_LP_IT_MSK_MASK … #define INT_MSK_PWRON_LP_IT_MSK_SHIFT … #define INT_MSK_PWRON_IT_MSK_MASK … #define INT_MSK_PWRON_IT_MSK_SHIFT … #define INT_MSK_VMBHI_IT_MSK_MASK … #define INT_MSK_VMBHI_IT_MSK_SHIFT … #define INT_MSK_PWRHOLD_F_IT_MSK_MASK … #define INT_MSK_PWRHOLD_F_IT_MSK_SHIFT … /*Register INT_STS2 (0x80) register.RegisterDescription */ #define INT_STS2_GPIO3_F_IT_MASK … #define INT_STS2_GPIO3_F_IT_SHIFT … #define INT_STS2_GPIO3_R_IT_MASK … #define INT_STS2_GPIO3_R_IT_SHIFT … #define INT_STS2_GPIO2_F_IT_MASK … #define INT_STS2_GPIO2_F_IT_SHIFT … #define INT_STS2_GPIO2_R_IT_MASK … #define INT_STS2_GPIO2_R_IT_SHIFT … #define INT_STS2_GPIO1_F_IT_MASK … #define INT_STS2_GPIO1_F_IT_SHIFT … #define INT_STS2_GPIO1_R_IT_MASK … #define INT_STS2_GPIO1_R_IT_SHIFT … #define INT_STS2_GPIO0_F_IT_MASK … #define INT_STS2_GPIO0_F_IT_SHIFT … #define INT_STS2_GPIO0_R_IT_MASK … #define INT_STS2_GPIO0_R_IT_SHIFT … /*Register INT_MSK2 (0x80) register.RegisterDescription */ #define INT_MSK2_GPIO3_F_IT_MSK_MASK … #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT … #define INT_MSK2_GPIO3_R_IT_MSK_MASK … #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT … #define INT_MSK2_GPIO2_F_IT_MSK_MASK … #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT … #define INT_MSK2_GPIO2_R_IT_MSK_MASK … #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT … #define INT_MSK2_GPIO1_F_IT_MSK_MASK … #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT … #define INT_MSK2_GPIO1_R_IT_MSK_MASK … #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT … #define INT_MSK2_GPIO0_F_IT_MSK_MASK … #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT … #define INT_MSK2_GPIO0_R_IT_MSK_MASK … #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT … /*Register INT_STS3 (0x80) register.RegisterDescription */ #define INT_STS3_PWRDN_IT_MASK … #define INT_STS3_PWRDN_IT_SHIFT … #define INT_STS3_VMBCH2_L_IT_MASK … #define INT_STS3_VMBCH2_L_IT_SHIFT … #define INT_STS3_VMBCH2_H_IT_MASK … #define INT_STS3_VMBCH2_H_IT_SHIFT … #define INT_STS3_WTCHDG_IT_MASK … #define INT_STS3_WTCHDG_IT_SHIFT … #define INT_STS3_GPIO5_F_IT_MASK … #define INT_STS3_GPIO5_F_IT_SHIFT … #define INT_STS3_GPIO5_R_IT_MASK … #define INT_STS3_GPIO5_R_IT_SHIFT … #define INT_STS3_GPIO4_F_IT_MASK … #define INT_STS3_GPIO4_F_IT_SHIFT … #define INT_STS3_GPIO4_R_IT_MASK … #define INT_STS3_GPIO4_R_IT_SHIFT … /*Register INT_MSK3 (0x80) register.RegisterDescription */ #define INT_MSK3_PWRDN_IT_MSK_MASK … #define INT_MSK3_PWRDN_IT_MSK_SHIFT … #define INT_MSK3_VMBCH2_L_IT_MSK_MASK … #define INT_MSK3_VMBCH2_L_IT_MSK_SHIFT … #define INT_MSK3_VMBCH2_H_IT_MSK_MASK … #define INT_MSK3_VMBCH2_H_IT_MSK_SHIFT … #define INT_MSK3_WTCHDG_IT_MSK_MASK … #define INT_MSK3_WTCHDG_IT_MSK_SHIFT … #define INT_MSK3_GPIO5_F_IT_MSK_MASK … #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT … #define INT_MSK3_GPIO5_R_IT_MSK_MASK … #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT … #define INT_MSK3_GPIO4_F_IT_MSK_MASK … #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT … #define INT_MSK3_GPIO4_R_IT_MSK_MASK … #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT … /*Register GPIO (0x80) register.RegisterDescription */ #define GPIO_SLEEP_MASK … #define GPIO_SLEEP_SHIFT … #define GPIO_DEB_MASK … #define GPIO_DEB_SHIFT … #define GPIO_PUEN_MASK … #define GPIO_PUEN_SHIFT … #define GPIO_CFG_MASK … #define GPIO_CFG_SHIFT … #define GPIO_STS_MASK … #define GPIO_STS_SHIFT … #define GPIO_SET_MASK … #define GPIO_SET_SHIFT … /*Register JTAGVERNUM (0x80) register.RegisterDescription */ #define JTAGVERNUM_VERNUM_MASK … #define JTAGVERNUM_VERNUM_SHIFT … /* Register VDDCTRL (0x27) bit definitions */ #define VDDCTRL_ST_MASK … #define VDDCTRL_ST_SHIFT … /*Register VDDCTRL_OP (0x28) bit definitions */ #define VDDCTRL_OP_CMD_MASK … #define VDDCTRL_OP_CMD_SHIFT … #define VDDCTRL_OP_SEL_MASK … #define VDDCTRL_OP_SEL_SHIFT … /*Register VDDCTRL_SR (0x29) bit definitions */ #define VDDCTRL_SR_SEL_MASK … #define VDDCTRL_SR_SEL_SHIFT … /* IRQ Definitions */ #define TPS65910_IRQ_VBAT_VMBDCH … #define TPS65910_IRQ_VBAT_VMHI … #define TPS65910_IRQ_PWRON … #define TPS65910_IRQ_PWRON_LP … #define TPS65910_IRQ_PWRHOLD … #define TPS65910_IRQ_HOTDIE … #define TPS65910_IRQ_RTC_ALARM … #define TPS65910_IRQ_RTC_PERIOD … #define TPS65910_IRQ_GPIO_R … #define TPS65910_IRQ_GPIO_F … #define TPS65910_NUM_IRQ … #define TPS65911_IRQ_PWRHOLD_F … #define TPS65911_IRQ_VBAT_VMHI … #define TPS65911_IRQ_PWRON … #define TPS65911_IRQ_PWRON_LP … #define TPS65911_IRQ_PWRHOLD_R … #define TPS65911_IRQ_HOTDIE … #define TPS65911_IRQ_RTC_ALARM … #define TPS65911_IRQ_RTC_PERIOD … #define TPS65911_IRQ_GPIO0_R … #define TPS65911_IRQ_GPIO0_F … #define TPS65911_IRQ_GPIO1_R … #define TPS65911_IRQ_GPIO1_F … #define TPS65911_IRQ_GPIO2_R … #define TPS65911_IRQ_GPIO2_F … #define TPS65911_IRQ_GPIO3_R … #define TPS65911_IRQ_GPIO3_F … #define TPS65911_IRQ_GPIO4_R … #define TPS65911_IRQ_GPIO4_F … #define TPS65911_IRQ_GPIO5_R … #define TPS65911_IRQ_GPIO5_F … #define TPS65911_IRQ_WTCHDG … #define TPS65911_IRQ_VMBCH2_H … #define TPS65911_IRQ_VMBCH2_L … #define TPS65911_IRQ_PWRDN … #define TPS65911_NUM_IRQ … /* GPIO Register Definitions */ #define TPS65910_GPIO_DEB … #define TPS65910_GPIO_PUEN … #define TPS65910_GPIO_CFG … #define TPS65910_GPIO_STS … #define TPS65910_GPIO_SET … /* Max number of TPS65910/11 GPIOs */ #define TPS65910_NUM_GPIO … #define TPS65911_NUM_GPIO … #define TPS6591X_MAX_NUM_GPIO … /* Regulator Index Definitions */ #define TPS65910_REG_VRTC … #define TPS65910_REG_VIO … #define TPS65910_REG_VDD1 … #define TPS65910_REG_VDD2 … #define TPS65910_REG_VDD3 … #define TPS65910_REG_VDIG1 … #define TPS65910_REG_VDIG2 … #define TPS65910_REG_VPLL … #define TPS65910_REG_VDAC … #define TPS65910_REG_VAUX1 … #define TPS65910_REG_VAUX2 … #define TPS65910_REG_VAUX33 … #define TPS65910_REG_VMMC … #define TPS65910_REG_VBB … #define TPS65911_REG_VDDCTRL … #define TPS65911_REG_LDO1 … #define TPS65911_REG_LDO2 … #define TPS65911_REG_LDO3 … #define TPS65911_REG_LDO4 … #define TPS65911_REG_LDO5 … #define TPS65911_REG_LDO6 … #define TPS65911_REG_LDO7 … #define TPS65911_REG_LDO8 … /* Max number of TPS65910/11 regulators */ #define TPS65910_NUM_REGS … /* External sleep controls through EN1/EN2/EN3/SLEEP inputs */ #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 … #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 … #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 … #define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP … /* * Sleep keepon data: Maintains the state in sleep mode * @therm_keepon: Keep on the thermal monitoring in sleep state. * @clkout32k_keepon: Keep on the 32KHz clock output in sleep state. * @i2chs_keepon: Keep on high speed internal clock in sleep state. */ struct tps65910_sleep_keepon_data { … }; /** * struct tps65910_board * Board platform data may be used to initialize regulators. */ struct tps65910_board { … }; /** * struct tps65910 - tps65910 sub-driver chip access routines */ struct tps65910 { … }; struct tps65910_platform_data { … }; static inline int tps65910_chip_id(struct tps65910 *tps65910) { … } #endif /* __LINUX_MFD_TPS65910_H */
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