// SPDX-License-Identifier: GPL-2.0-only /* * Calxeda Highbank AHCI SATA platform driver * Copyright 2012 Calxeda, Inc. * * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov */ #include <linux/kernel.h> #include <linux/gfp.h> #include <linux/module.h> #include <linux/types.h> #include <linux/err.h> #include <linux/io.h> #include <linux/spinlock.h> #include <linux/device.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/platform_device.h> #include <linux/libata.h> #include <linux/interrupt.h> #include <linux/delay.h> #include <linux/export.h> #include <linux/gpio/consumer.h> #include "ahci.h" #define CPHY_MAP(dev, addr) … #define CPHY_ADDR(addr) … #define SERDES_CR_CTL … #define SERDES_CR_ADDR … #define SERDES_CR_DATA … #define CR_BUSY … #define CR_START … #define CR_WR_RDN … #define CPHY_TX_INPUT_STS … #define CPHY_RX_INPUT_STS … #define CPHY_SATA_TX_OVERRIDE … #define CPHY_SATA_RX_OVERRIDE … #define CPHY_TX_OVERRIDE … #define CPHY_RX_OVERRIDE … #define SPHY_LANE … #define SPHY_HALF_RATE … #define CPHY_SATA_DPLL_MODE … #define CPHY_SATA_DPLL_SHIFT … #define CPHY_SATA_DPLL_RESET … #define CPHY_SATA_TX_ATTEN … #define CPHY_SATA_TX_ATTEN_SHIFT … #define CPHY_PHY_COUNT … #define CPHY_LANE_COUNT … #define CPHY_PORT_COUNT … static DEFINE_SPINLOCK(cphy_lock); /* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based * sata ports to their phys and then to their lanes within the phys */ struct phy_lane_info { … }; static struct phy_lane_info port_data[CPHY_PORT_COUNT]; static DEFINE_SPINLOCK(sgpio_lock); #define SCLOCK … #define SLOAD … #define SDATA … #define SGPIO_PINS … #define SGPIO_PORTS … struct ecx_plat_data { … }; #define SGPIO_SIGNALS … #define ECX_ACTIVITY_BITS … #define ECX_ACTIVITY_SHIFT … #define ECX_LOCATE_BITS … #define ECX_LOCATE_SHIFT … #define ECX_FAULT_BITS … #define ECX_FAULT_SHIFT … static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port, u32 shift) { … } static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state) { … } /* * Tell the LED controller that the signal has changed by raising the clock * line for 50 uS and then lowering it for 50 uS. */ static void ecx_led_cycle_clock(struct ecx_plat_data *pdata) { … } static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state, ssize_t size) { … } static void highbank_set_em_messages(struct device *dev, struct ahci_host_priv *hpriv, struct ata_port_info *pi) { … } static u32 __combo_phy_reg_read(u8 sata_port, u32 addr) { … } static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data) { … } static void combo_phy_wait_for_ready(u8 sata_port) { … } static u32 combo_phy_read(u8 sata_port, u32 addr) { … } static void combo_phy_write(u8 sata_port, u32 addr, u32 data) { … } static void highbank_cphy_disable_overrides(u8 sata_port) { … } static void cphy_override_tx_attenuation(u8 sata_port, u32 val) { … } static void cphy_override_rx_mode(u8 sata_port, u32 val) { … } static void highbank_cphy_override_lane(u8 sata_port) { … } static int highbank_initialize_phys(struct device *dev, void __iomem *addr) { … } /* * The Calxeda SATA phy intermittently fails to bring up a link with Gen3 * Retrying the phy hard reset can work around the issue, but the drive * may fail again. In less than 150 out of 15000 test runs, it took more * than 10 tries for the link to be established (but never more than 35). * Triple the maximum observed retry count to provide plenty of margin for * rare events and to guarantee that the link is established. * * Also, the default 2 second time-out on a failed drive is too long in * this situation. The uboot implementation of the same driver function * uses a much shorter time-out period and never experiences a time out * issue. Reducing the time-out to 500ms improves the responsiveness. * The other timing constants were kept the same as the stock AHCI driver. * This change was also tested 15000 times on 24 drives and none of them * experienced a time out. */ static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class, unsigned long deadline) { … } static struct ata_port_operations ahci_highbank_ops = …; static const struct ata_port_info ahci_highbank_port_info = …; static const struct scsi_host_template ahci_highbank_platform_sht = …; static const struct of_device_id ahci_of_match[] = …; MODULE_DEVICE_TABLE(of, ahci_of_match); static int ahci_highbank_probe(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int ahci_highbank_suspend(struct device *dev) { … } static int ahci_highbank_resume(struct device *dev) { … } #endif static SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops, ahci_highbank_suspend, ahci_highbank_resume); static struct platform_driver ahci_highbank_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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