/* * drivers/ata/pata_arasan_cf.c * * Arasan Compact Flash host controller source file * * Copyright (C) 2011 ST Microelectronics * Viresh Kumar <[email protected]> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ /* * The Arasan CompactFlash Device Controller IP core has three basic modes of * operation: PC card ATA using I/O mode, PC card ATA using memory mode, PC card * ATA using true IDE modes. This driver supports only True IDE mode currently. * * Arasan CF Controller shares global irq register with Arasan XD Controller. * * Tested on arch/arm/mach-spear13xx */ #include <linux/ata.h> #include <linux/clk.h> #include <linux/completion.h> #include <linux/delay.h> #include <linux/dmaengine.h> #include <linux/io.h> #include <linux/irq.h> #include <linux/kernel.h> #include <linux/libata.h> #include <linux/module.h> #include <linux/of.h> #include <linux/pata_arasan_cf_data.h> #include <linux/platform_device.h> #include <linux/pm.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/types.h> #include <linux/workqueue.h> #include <trace/events/libata.h> #define DRIVER_NAME … #define TIMEOUT … /* Registers */ /* CompactFlash Interface Status */ #define CFI_STS … #define STS_CHG … #define BIN_AUDIO_OUT … #define CARD_DETECT1 … #define CARD_DETECT2 … #define INP_ACK … #define CARD_READY … #define IO_READY … #define B16_IO_PORT_SEL … /* IRQ */ #define IRQ_STS … /* Interrupt Enable */ #define IRQ_EN … #define CARD_DETECT_IRQ … #define STATUS_CHNG_IRQ … #define MEM_MODE_IRQ … #define IO_MODE_IRQ … #define TRUE_IDE_MODE_IRQ … #define PIO_XFER_ERR_IRQ … #define BUF_AVAIL_IRQ … #define XFER_DONE_IRQ … #define IGNORED_IRQS … #define TRUE_IDE_IRQS … /* Operation Mode */ #define OP_MODE … #define CARD_MODE_MASK … #define MEM_MODE … #define IO_MODE … #define TRUE_IDE_MODE … #define CARD_TYPE_MASK … #define CF_CARD … #define CF_PLUS_CARD … #define CARD_RESET … #define CFHOST_ENB … #define OUTPUTS_TRISTATE … #define ULTRA_DMA_ENB … #define MULTI_WORD_DMA_ENB … #define DRQ_BLOCK_SIZE_MASK … #define DRQ_BLOCK_SIZE_512 … #define DRQ_BLOCK_SIZE_1024 … #define DRQ_BLOCK_SIZE_2048 … #define DRQ_BLOCK_SIZE_4096 … /* CF Interface Clock Configuration */ #define CLK_CFG … #define CF_IF_CLK_MASK … /* CF Timing Mode Configuration */ #define TM_CFG … #define MEM_MODE_TIMING_MASK … #define MEM_MODE_TIMING_250NS … #define MEM_MODE_TIMING_120NS … #define MEM_MODE_TIMING_100NS … #define MEM_MODE_TIMING_80NS … #define IO_MODE_TIMING_MASK … #define IO_MODE_TIMING_250NS … #define IO_MODE_TIMING_120NS … #define IO_MODE_TIMING_100NS … #define IO_MODE_TIMING_80NS … #define TRUEIDE_PIO_TIMING_MASK … #define TRUEIDE_PIO_TIMING_SHIFT … #define TRUEIDE_MWORD_DMA_TIMING_MASK … #define TRUEIDE_MWORD_DMA_TIMING_SHIFT … #define ULTRA_DMA_TIMING_MASK … #define ULTRA_DMA_TIMING_SHIFT … /* CF Transfer Address */ #define XFER_ADDR … #define XFER_ADDR_MASK … #define MAX_XFER_COUNT … /* Transfer Control */ #define XFER_CTR … #define XFER_COUNT_MASK … #define ADDR_INC_DISABLE … #define XFER_WIDTH_MASK … #define XFER_WIDTH_8B … #define XFER_WIDTH_16B … #define MEM_TYPE_MASK … #define MEM_TYPE_COMMON … #define MEM_TYPE_ATTRIBUTE … #define MEM_IO_XFER_MASK … #define MEM_XFER … #define IO_XFER … #define DMA_XFER_MODE … #define AHB_BUS_NORMAL_PIO_OPRTN … #define XFER_DIR_MASK … #define XFER_READ … #define XFER_WRITE … #define XFER_START … /* Write Data Port */ #define WRITE_PORT … /* Read Data Port */ #define READ_PORT … /* ATA Data Port */ #define ATA_DATA_PORT … #define ATA_DATA_PORT_MASK … /* ATA Error/Features */ #define ATA_ERR_FTR … /* ATA Sector Count */ #define ATA_SC … /* ATA Sector Number */ #define ATA_SN … /* ATA Cylinder Low */ #define ATA_CL … /* ATA Cylinder High */ #define ATA_CH … /* ATA Select Card/Head */ #define ATA_SH … /* ATA Status-Command */ #define ATA_STS_CMD … /* ATA Alternate Status/Device Control */ #define ATA_ASTS_DCTR … /* Extended Write Data Port 0x200-0x3FC */ #define EXT_WRITE_PORT … /* Extended Read Data Port 0x400-0x5FC */ #define EXT_READ_PORT … #define FIFO_SIZE … /* Global Interrupt Status */ #define GIRQ_STS … /* Global Interrupt Status enable */ #define GIRQ_STS_EN … /* Global Interrupt Signal enable */ #define GIRQ_SGN_EN … #define GIRQ_CF … #define GIRQ_XD … /* Compact Flash Controller Dev Structure */ struct arasan_cf_dev { … }; static const struct scsi_host_template arasan_cf_sht = …; static void cf_dumpregs(struct arasan_cf_dev *acdev) { … } /* Enable/Disable global interrupts shared between CF and XD ctrlr. */ static void cf_ginterrupt_enable(struct arasan_cf_dev *acdev, bool enable) { … } /* Enable/Disable CF interrupts */ static inline void cf_interrupt_enable(struct arasan_cf_dev *acdev, u32 mask, bool enable) { … } static inline void cf_card_reset(struct arasan_cf_dev *acdev) { … } static inline void cf_ctrl_reset(struct arasan_cf_dev *acdev) { … } static void cf_card_detect(struct arasan_cf_dev *acdev, bool hotplugged) { … } static int cf_init(struct arasan_cf_dev *acdev) { … } static void cf_exit(struct arasan_cf_dev *acdev) { … } static void dma_callback(void *dev) { … } static inline void dma_complete(struct arasan_cf_dev *acdev) { … } static inline int wait4buf(struct arasan_cf_dev *acdev) { … } static int dma_xfer(struct arasan_cf_dev *acdev, dma_addr_t src, dma_addr_t dest, u32 len) { … } static int sg_xfer(struct arasan_cf_dev *acdev, struct scatterlist *sg) { … } /* * This routine uses External DMA controller to read/write data to FIFO of CF * controller. There are two xfer related interrupt supported by CF controller: * - buf_avail: This interrupt is generated as soon as we have buffer of 512 * bytes available for reading or empty buffer available for writing. * - xfer_done: This interrupt is generated on transfer of "xfer_size" amount of * data to/from FIFO. xfer_size is programmed in XFER_CTR register. * * Max buffer size = FIFO_SIZE = 512 Bytes. * Max xfer_size = MAX_XFER_COUNT = 256 KB. */ static void data_xfer(struct work_struct *work) { … } static void delayed_finish(struct work_struct *work) { … } static irqreturn_t arasan_cf_interrupt(int irq, void *dev) { … } static void arasan_cf_freeze(struct ata_port *ap) { … } static void arasan_cf_error_handler(struct ata_port *ap) { … } static void arasan_cf_dma_start(struct arasan_cf_dev *acdev) { … } static unsigned int arasan_cf_qc_issue(struct ata_queued_cmd *qc) { … } static void arasan_cf_set_piomode(struct ata_port *ap, struct ata_device *adev) { … } static void arasan_cf_set_dmamode(struct ata_port *ap, struct ata_device *adev) { … } static struct ata_port_operations arasan_cf_ops = …; static int arasan_cf_probe(struct platform_device *pdev) { … } static void arasan_cf_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int arasan_cf_suspend(struct device *dev) { … } static int arasan_cf_resume(struct device *dev) { … } #endif static SIMPLE_DEV_PM_OPS(arasan_cf_pm_ops, arasan_cf_suspend, arasan_cf_resume); #ifdef CONFIG_OF static const struct of_device_id arasan_cf_id_table[] = …; MODULE_DEVICE_TABLE(of, arasan_cf_id_table); #endif static struct platform_driver arasan_cf_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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