linux/drivers/ata/sata_qstor.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  sata_qstor.c - Pacific Digital Corporation QStor SATA
 *
 *  Maintained by:  Mark Lord <[email protected]>
 *
 *  Copyright 2005 Pacific Digital Corporation.
 *  (OSL/GPL code release authorized by Jalil Fadavi).
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/driver-api/libata.rst
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/gfp.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME
#define DRV_VERSION

enum {};

enum {};

qs_state_t;

struct qs_port_priv {};

static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
static int qs_port_start(struct ata_port *ap);
static void qs_host_stop(struct ata_host *host);
static enum ata_completion_errors qs_qc_prep(struct ata_queued_cmd *qc);
static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
static void qs_freeze(struct ata_port *ap);
static void qs_thaw(struct ata_port *ap);
static int qs_prereset(struct ata_link *link, unsigned long deadline);
static void qs_error_handler(struct ata_port *ap);

static const struct scsi_host_template qs_ata_sht =;

static struct ata_port_operations qs_ata_ops =;

static const struct ata_port_info qs_port_info[] =;

static const struct pci_device_id qs_ata_pci_tbl[] =;

static struct pci_driver qs_ata_pci_driver =;

static void __iomem *qs_mmio_base(struct ata_host *host)
{}

static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
{}

static inline void qs_enter_reg_mode(struct ata_port *ap)
{}

static inline void qs_reset_channel_logic(struct ata_port *ap)
{}

static void qs_freeze(struct ata_port *ap)
{}

static void qs_thaw(struct ata_port *ap)
{}

static int qs_prereset(struct ata_link *link, unsigned long deadline)
{}

static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
{}

static void qs_error_handler(struct ata_port *ap)
{}

static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
{}

static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
{}

static enum ata_completion_errors qs_qc_prep(struct ata_queued_cmd *qc)
{}

static inline void qs_packet_start(struct ata_queued_cmd *qc)
{}

static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
{}

static void qs_do_or_die(struct ata_queued_cmd *qc, u8 status)
{}

static inline unsigned int qs_intr_pkt(struct ata_host *host)
{}

static inline unsigned int qs_intr_mmio(struct ata_host *host)
{}

static irqreturn_t qs_intr(int irq, void *dev_instance)
{}

static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
{}

static int qs_port_start(struct ata_port *ap)
{}

static void qs_host_stop(struct ata_host *host)
{}

static void qs_host_init(struct ata_host *host, unsigned int chip_id)
{}

/*
 * The QStor understands 64-bit buses, and uses 64-bit fields
 * for DMA pointers regardless of bus width.  We just have to
 * make sure our DMA masks are set appropriately for whatever
 * bridge lies between us and the QStor, and then the DMA mapping
 * code will ensure we only ever "see" appropriate buffer addresses.
 * If we're 32-bit limited somewhere, then our 64-bit fields will
 * just end up with zeros in the upper 32-bits, without any special
 * logic required outside of this routine (below).
 */
static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
{}

static int qs_ata_init_one(struct pci_dev *pdev,
				const struct pci_device_id *ent)
{}

module_pci_driver();

MODULE_AUTHOR();
MODULE_DESCRIPTION();
MODULE_LICENSE();
MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
MODULE_VERSION();