// SPDX-License-Identifier: GPL-2.0-only /* * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers. * * This driver is heavily based upon: * * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 * * Copyright (C) 1999-2003 Andre Hedrick <[email protected]> * Portions Copyright (C) 2001 Sun Microsystems, Inc. * Portions Copyright (C) 2003 Red Hat Inc * * * TODO * Look into engine reset on timeout errors. Should not be required. */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/blkdev.h> #include <linux/delay.h> #include <scsi/scsi_host.h> #include <linux/libata.h> #define DRV_NAME … #define DRV_VERSION … struct hpt_clock { … }; /* key for bus clock timings * bit * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. * cycles = value + 1 * 4:7 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. * cycles = value + 1 * 8:11 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file * register access. * 12:15 cmd_low_time. Active time of DIOW_/DIOR_ during task file * register access. * 16:18 udma_cycle_time. Clock cycles for UDMA xfer? * 19:21 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. * 22:24 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file * register access. * 28 UDMA enable. * 29 DMA enable. * 30 PIO_MST enable. If set, the chip is in bus master mode during * PIO xfer. * 31 FIFO enable. */ static const struct hpt_clock hpt366_40[] = …; static const struct hpt_clock hpt366_33[] = …; static const struct hpt_clock hpt366_25[] = …; /** * hpt36x_find_mode - find the hpt36x timing * @ap: ATA port * @speed: transfer mode * * Return the 32bit register programming information for this channel * that matches the speed provided. */ static u32 hpt36x_find_mode(struct ata_port *ap, int speed) { … } static const char * const bad_ata33[] = …; static const char * const bad_ata66_4[] = …; static const char * const bad_ata66_3[] = …; static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char * const list[]) { … } /** * hpt366_filter - mode selection filter * @adev: ATA device * @mask: Current mask to manipulate and pass back * * Block UDMA on devices that cause trouble with this controller. */ static unsigned int hpt366_filter(struct ata_device *adev, unsigned int mask) { … } static int hpt36x_cable_detect(struct ata_port *ap) { … } static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode) { … } /** * hpt366_set_piomode - PIO setup * @ap: ATA interface * @adev: device on the interface * * Perform PIO mode setup. */ static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev) { … } /** * hpt366_set_dmamode - DMA timing setup * @ap: ATA interface * @adev: Device being configured * * Set up the channel for MWDMA or UDMA modes. Much the same as with * PIO, load the mode number and then set MWDMA or UDMA flag. */ static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev) { … } /** * hpt366_prereset - reset the hpt36x bus * @link: ATA link to reset * @deadline: deadline jiffies for the operation * * Perform the initial reset handling for the 36x series controllers. * Reset the hardware and state machine, */ static int hpt366_prereset(struct ata_link *link, unsigned long deadline) { … } static const struct scsi_host_template hpt36x_sht = …; /* * Configuration for HPT366/68 */ static struct ata_port_operations hpt366_port_ops = …; /** * hpt36x_init_chipset - common chip setup * @dev: PCI device * * Perform the chip setup work that must be done at both init and * resume time */ static void hpt36x_init_chipset(struct pci_dev *dev) { … } /** * hpt36x_init_one - Initialise an HPT366/368 * @dev: PCI device * @id: Entry in match table * * Initialise an HPT36x device. There are some interesting complications * here. Firstly the chip may report 366 and be one of several variants. * Secondly all the timings depend on the clock for the chip which we must * detect and look up * * This is the known chip mappings. It may be missing a couple of later * releases. * * Chip version PCI Rev Notes * HPT366 4 (HPT366) 0 UDMA66 * HPT366 4 (HPT366) 1 UDMA66 * HPT368 4 (HPT366) 2 UDMA66 * HPT37x/30x 4 (HPT366) 3+ Other driver * */ static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id) { … } #ifdef CONFIG_PM_SLEEP static int hpt36x_reinit_one(struct pci_dev *dev) { … } #endif static const struct pci_device_id hpt36x[] = …; static struct pci_driver hpt36x_pci_driver = …; module_pci_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_DEVICE_TABLE(pci, hpt36x); MODULE_VERSION(…);
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