// SPDX-License-Identifier: GPL-2.0-only /* * pata_ns87415.c - NS87415 (and PARISC SUPERIO 87560) PATA * * (C) 2005 Red Hat <[email protected]> * * This is a fairly generic MWDMA controller. It has some limitations * as it requires timing reloads on PIO/DMA transitions but it is otherwise * fairly well designed. * * This driver assumes the firmware has left the chip in a valid ST506 * compliant state, either legacy IRQ 14/15 or native INTA shared. You * may need to add platform code if your system fails to do this. * * The same cell appears in the 87560 controller used by some PARISC * systems. This has its own special mountain of errata. * * TODO: * Get someone to test on SPARC * Implement lazy pio/dma switching for better performance * 8bit shared timing. * See if we need to kill the FIFO for ATAPI */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/blkdev.h> #include <linux/delay.h> #include <linux/device.h> #include <scsi/scsi_host.h> #include <linux/libata.h> #include <linux/ata.h> #define DRV_NAME … #define DRV_VERSION … /** * ns87415_set_mode - Initialize host controller mode timings * @ap: Port whose timings we are configuring * @adev: Device whose timings we are configuring * @mode: Mode to set * * Program the mode registers for this controller, channel and * device. Because the chip is quite an old design we have to do this * for PIO/DMA switches. * * LOCKING: * None (inherited from caller). */ static void ns87415_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode) { … } /** * ns87415_set_piomode - Initialize host controller PATA PIO timings * @ap: Port whose timings we are configuring * @adev: Device to program * * Set PIO mode for device, in host controller PCI config space. * * LOCKING: * None (inherited from caller). */ static void ns87415_set_piomode(struct ata_port *ap, struct ata_device *adev) { … } /** * ns87415_bmdma_setup - Set up DMA * @qc: Command block * * Set up for bus mastering DMA. We have to do this ourselves * rather than use the helper due to a chip erratum */ static void ns87415_bmdma_setup(struct ata_queued_cmd *qc) { … } /** * ns87415_bmdma_start - Begin DMA transfer * @qc: Command block * * Switch the timings for the chip and set up for a DMA transfer * before the DMA burst begins. * * FIXME: We should do lazy switching on bmdma_start versus * ata_pio_data_xfer for better performance. */ static void ns87415_bmdma_start(struct ata_queued_cmd *qc) { … } /** * ns87415_bmdma_stop - End DMA transfer * @qc: Command block * * End DMA mode and switch the controller back into PIO mode */ static void ns87415_bmdma_stop(struct ata_queued_cmd *qc) { … } /** * ns87415_irq_clear - Clear interrupt * @ap: Channel to clear * * Erratum: Due to a chip bug registers 02 and 0A bit 1 and 2 (the * error bits) are reset by writing to register 00 or 08. */ static void ns87415_irq_clear(struct ata_port *ap) { … } /** * ns87415_check_atapi_dma - ATAPI DMA filter * @qc: Command block * * Disable ATAPI DMA (for now). We may be able to do DMA if we * kill the prefetching. This isn't clear. */ static int ns87415_check_atapi_dma(struct ata_queued_cmd *qc) { … } #if defined(CONFIG_SUPERIO) /* SUPERIO 87560 is a PoS chip that NatSem denies exists. * Unfortunately, it's built-in on all Astro-based PA-RISC workstations * which use the integrated NS87514 cell for CD-ROM support. * i.e we have to support for CD-ROM installs. * See drivers/parisc/superio.c for more gory details. * * Workarounds taken from drivers/ide/pci/ns87415.c */ #include <asm/superio.h> #define SUPERIO_IDE_MAX_RETRIES … /** * ns87560_read_buggy - workaround buggy Super I/O chip * @port: Port to read * * Work around chipset problems in the 87560 SuperIO chip */ static u8 ns87560_read_buggy(void __iomem *port) { u8 tmp; int retries = SUPERIO_IDE_MAX_RETRIES; do { tmp = ioread8(port); if (tmp != 0) return tmp; udelay(50); } while(retries-- > 0); return tmp; } /** * ns87560_check_status * @ap: channel to check * * Return the status of the channel working around the * 87560 flaws. */ static u8 ns87560_check_status(struct ata_port *ap) { return ns87560_read_buggy(ap->ioaddr.status_addr); } /** * ns87560_tf_read - input device's ATA taskfile shadow registers * @ap: Port from which input is read * @tf: ATA taskfile register set for storing input * * Reads ATA taskfile registers for currently-selected device * into @tf. Work around the 87560 bugs. * * LOCKING: * Inherited from caller. */ static void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf) { struct ata_ioports *ioaddr = &ap->ioaddr; tf->status = ns87560_check_status(ap); tf->error = ioread8(ioaddr->error_addr); tf->nsect = ioread8(ioaddr->nsect_addr); tf->lbal = ioread8(ioaddr->lbal_addr); tf->lbam = ioread8(ioaddr->lbam_addr); tf->lbah = ioread8(ioaddr->lbah_addr); tf->device = ns87560_read_buggy(ioaddr->device_addr); if (tf->flags & ATA_TFLAG_LBA48) { iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); tf->hob_feature = ioread8(ioaddr->error_addr); tf->hob_nsect = ioread8(ioaddr->nsect_addr); tf->hob_lbal = ioread8(ioaddr->lbal_addr); tf->hob_lbam = ioread8(ioaddr->lbam_addr); tf->hob_lbah = ioread8(ioaddr->lbah_addr); iowrite8(tf->ctl, ioaddr->ctl_addr); ap->last_ctl = tf->ctl; } } /** * ns87560_bmdma_status * @ap: channel to check * * Return the DMA status of the channel working around the * 87560 flaws. */ static u8 ns87560_bmdma_status(struct ata_port *ap) { return ns87560_read_buggy(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); } #endif /* 87560 SuperIO Support */ static struct ata_port_operations ns87415_pata_ops = …; #if defined(CONFIG_SUPERIO) static struct ata_port_operations ns87560_pata_ops = { .inherits = &ns87415_pata_ops, .sff_tf_read = ns87560_tf_read, .sff_check_status = ns87560_check_status, .bmdma_status = ns87560_bmdma_status, }; #endif static const struct scsi_host_template ns87415_sht = …; static void ns87415_fixup(struct pci_dev *pdev) { … } /** * ns87415_init_one - Register 87415 ATA PCI device with kernel services * @pdev: PCI device to register * @ent: Entry in ns87415_pci_tbl matching with @pdev * * Called from kernel PCI layer. We probe for combined mode (sigh), * and then hand over control to libata, for it to do the rest. * * LOCKING: * Inherited from PCI layer (may sleep). * * RETURNS: * Zero on success, or -ERRNO value. */ static int ns87415_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) { … } static const struct pci_device_id ns87415_pci_tbl[] = …; #ifdef CONFIG_PM_SLEEP static int ns87415_reinit_one(struct pci_dev *pdev) { … } #endif static struct pci_driver ns87415_pci_driver = …; module_pci_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl); MODULE_VERSION(…);
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