// SPDX-License-Identifier: GPL-2.0 /* * Intel Whiskey Cove PMIC GPIO Driver * * This driver is written based on gpio-crystalcove.c * * Copyright (C) 2016 Intel Corporation. All rights reserved. */ #include <linux/bitops.h> #include <linux/gpio/driver.h> #include <linux/interrupt.h> #include <linux/mfd/intel_soc_pmic.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/seq_file.h> /* * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks: * Bank 0: Pin 0 - 6 * Bank 1: Pin 7 - 10 * Bank 2: Pin 11 - 12 * Each pin has one output control register and one input control register. */ #define BANK0_NR_PINS … #define BANK1_NR_PINS … #define BANK2_NR_PINS … #define WCOVE_GPIO_NUM … #define WCOVE_VGPIO_NUM … /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */ #define GPIO_OUT_CTRL_BASE … /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */ #define GPIO_IN_CTRL_BASE … /* * GPIO interrupts are organized in two groups: * Group 0: Bank 0 pins (Pin 0 - 6) * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12) * Each group has two registers (one bit per pin): status and mask. */ #define GROUP0_NR_IRQS … #define GROUP1_NR_IRQS … #define IRQ_MASK_BASE … #define IRQ_STATUS_BASE … #define GPIO_IRQ0_MASK … #define GPIO_IRQ1_MASK … #define UPDATE_IRQ_TYPE … #define UPDATE_IRQ_MASK … #define CTLI_INTCNT_DIS … #define CTLI_INTCNT_NE … #define CTLI_INTCNT_PE … #define CTLI_INTCNT_BE … #define CTLO_DIR_IN … #define CTLO_DIR_OUT … #define CTLO_DRV_MASK … #define CTLO_DRV_OD … #define CTLO_DRV_CMOS … #define CTLO_DRV_REN … #define CTLO_RVAL_2KDOWN … #define CTLO_RVAL_2KUP … #define CTLO_RVAL_50KDOWN … #define CTLO_RVAL_50KUP … #define CTLO_INPUT_SET … #define CTLO_OUTPUT_SET … enum ctrl_register { … }; /* * struct wcove_gpio - Whiskey Cove GPIO controller * @buslock: for bus lock/sync and unlock. * @chip: the abstract gpio_chip structure. * @dev: the gpio device * @regmap: the regmap from the parent device. * @regmap_irq_chip: the regmap of the gpio irq chip. * @update: pending IRQ setting update, to be written to the chip upon unlock. * @intcnt: the Interrupt Detect value to be written. * @set_irq_mask: true if the IRQ mask needs to be set, false to clear. */ struct wcove_gpio { … }; static inline int to_reg(int gpio, enum ctrl_register type) { … } static inline int to_ireg(int gpio, enum ctrl_register type, unsigned int *mask) { … } static void wcove_update_irq_mask(struct wcove_gpio *wg, irq_hw_number_t gpio) { … } static void wcove_update_irq_ctrl(struct wcove_gpio *wg, irq_hw_number_t gpio) { … } static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio) { … } static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, int value) { … } static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) { … } static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio) { … } static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) { … } static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio, unsigned long config) { … } static int wcove_irq_type(struct irq_data *data, unsigned int type) { … } static void wcove_bus_lock(struct irq_data *data) { … } static void wcove_bus_sync_unlock(struct irq_data *data) { … } static void wcove_irq_unmask(struct irq_data *data) { … } static void wcove_irq_mask(struct irq_data *data) { … } static const struct irq_chip wcove_irqchip = …; static irqreturn_t wcove_gpio_irq_handler(int irq, void *data) { … } static void wcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) { … } static int wcove_gpio_probe(struct platform_device *pdev) { … } /* * Whiskey Cove PMIC itself is a analog device(but with digital control * interface) providing power management support for other devices in * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver. */ static struct platform_driver wcove_gpio_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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