// SPDX-License-Identifier: GPL-2.0-or-later /* sc520cdp.c -- MTD map driver for AMD SC520 Customer Development Platform * * Copyright (C) 2001 Sysgo Real-Time Solutions GmbH * * The SC520CDP is an evaluation board for the Elan SC520 processor available * from AMD. It has two banks of 32-bit Flash ROM, each 8 Megabytes in size, * and up to 512 KiB of 8-bit DIL Flash ROM. * For details see https://www.amd.com/products/epd/desiging/evalboards/18.elansc520/520_cdp_brief/index.html */ #include <linux/module.h> #include <linux/types.h> #include <linux/kernel.h> #include <linux/init.h> #include <asm/io.h> #include <linux/mtd/mtd.h> #include <linux/mtd/map.h> #include <linux/mtd/concat.h> /* ** The Embedded Systems BIOS decodes the first FLASH starting at ** 0x8400000. This is a *terrible* place for it because accessing ** the flash at this location causes the A22 address line to be high ** (that's what 0x8400000 binary's ought to be). But this is the highest ** order address line on the raw flash devices themselves!! ** This causes the top HALF of the flash to be accessed first. Beyond ** the physical limits of the flash, the flash chip aliases over (to ** 0x880000 which causes the bottom half to be accessed. This splits the ** flash into two and inverts it! If you then try to access this from another ** program that does NOT do this insanity, then you *will* access the ** first half of the flash, but not find what you expect there. That ** stuff is in the *second* half! Similarly, the address used by the ** BIOS for the second FLASH bank is also quite a bad choice. ** If REPROGRAM_PAR is defined below (the default), then this driver will ** choose more useful addresses for the FLASH banks by reprogramming the ** responsible PARxx registers in the SC520's MMCR region. This will ** cause the settings to be incompatible with the BIOS's settings, which ** shouldn't be a problem since you are running Linux, (i.e. the BIOS is ** not much use anyway). However, if you need to be compatible with ** the BIOS for some reason, just undefine REPROGRAM_PAR. */ #define REPROGRAM_PAR #ifdef REPROGRAM_PAR /* These are the addresses we want.. */ #define WINDOW_ADDR_0 … #define WINDOW_ADDR_1 … #define WINDOW_ADDR_2 … /* .. and these are the addresses the BIOS gives us */ #define WINDOW_ADDR_0_BIOS … #define WINDOW_ADDR_1_BIOS … #define WINDOW_ADDR_2_BIOS … #else #define WINDOW_ADDR_0 … #define WINDOW_ADDR_1 … #define WINDOW_ADDR_2 … #endif #define WINDOW_SIZE_0 … #define WINDOW_SIZE_1 … #define WINDOW_SIZE_2 … static struct map_info sc520cdp_map[] = …; #define NUM_FLASH_BANKS … static struct mtd_info *mymtd[NUM_FLASH_BANKS]; static struct mtd_info *merged_mtd; #ifdef REPROGRAM_PAR /* ** The SC520 MMCR (memory mapped control register) region resides ** at 0xFFFEF000. The 16 Programmable Address Region (PAR) registers ** are at offset 0x88 in the MMCR: */ #define SC520_MMCR_BASE … #define SC520_MMCR_EXTENT … #define SC520_PAR(x) … #define NUM_SC520_PAR … /* ** The highest three bits in a PAR register determine what target ** device is controlled by this PAR. Here, only ROMCS? and BOOTCS ** devices are of interest. */ #define SC520_PAR_BOOTCS … #define SC520_PAR_ROMCS0 … #define SC520_PAR_ROMCS1 … #define SC520_PAR_TRGDEV … /* ** Bits 28 thru 26 determine some attributes for the ** region controlled by the PAR. (We only use non-cacheable) */ #define SC520_PAR_WRPROT … #define SC520_PAR_NOCACHE … #define SC520_PAR_NOEXEC … /* ** Bit 25 determines the granularity: 4K or 64K */ #define SC520_PAR_PG_SIZ4 … #define SC520_PAR_PG_SIZ64 … /* ** Build a value to be written into a PAR register. ** We only need ROM entries, 64K page size: */ #define SC520_PAR_ENTRY(trgdev, address, size) … struct sc520_par_table { … }; static const struct sc520_par_table par_table[NUM_FLASH_BANKS] = …; static void sc520cdp_setup_par(void) { … } #endif static int __init init_sc520cdp(void) { … } static void __exit cleanup_sc520cdp(void) { … } module_init(…) …; module_exit(cleanup_sc520cdp); MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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