/* SPDX-License-Identifier: GPL-2.0-only */ /* * linux/include/linux/mtd/onenand_regs.h * * OneNAND Register header file * * Copyright (C) 2005-2007 Samsung Electronics * Kyungmin Park <[email protected]> */ #ifndef __ONENAND_REG_H #define __ONENAND_REG_H /* Memory Address Map Translation (Word order) */ #define ONENAND_MEMORY_MAP(x) … /* * External BufferRAM area */ #define ONENAND_BOOTRAM … #define ONENAND_DATARAM … #define ONENAND_SPARERAM … /* * OneNAND Registers */ #define ONENAND_REG_MANUFACTURER_ID … #define ONENAND_REG_DEVICE_ID … #define ONENAND_REG_VERSION_ID … #define ONENAND_REG_DATA_BUFFER_SIZE … #define ONENAND_REG_BOOT_BUFFER_SIZE … #define ONENAND_REG_NUM_BUFFERS … #define ONENAND_REG_TECHNOLOGY … #define ONENAND_REG_START_ADDRESS1 … #define ONENAND_REG_START_ADDRESS2 … #define ONENAND_REG_START_ADDRESS3 … #define ONENAND_REG_START_ADDRESS4 … #define ONENAND_REG_START_ADDRESS5 … #define ONENAND_REG_START_ADDRESS6 … #define ONENAND_REG_START_ADDRESS7 … #define ONENAND_REG_START_ADDRESS8 … #define ONENAND_REG_START_BUFFER … #define ONENAND_REG_COMMAND … #define ONENAND_REG_SYS_CFG1 … #define ONENAND_REG_SYS_CFG2 … #define ONENAND_REG_CTRL_STATUS … #define ONENAND_REG_INTERRUPT … #define ONENAND_REG_START_BLOCK_ADDRESS … #define ONENAND_REG_END_BLOCK_ADDRESS … #define ONENAND_REG_WP_STATUS … #define ONENAND_REG_ECC_STATUS … #define ONENAND_REG_ECC_M0 … #define ONENAND_REG_ECC_S0 … #define ONENAND_REG_ECC_M1 … #define ONENAND_REG_ECC_S1 … #define ONENAND_REG_ECC_M2 … #define ONENAND_REG_ECC_S2 … #define ONENAND_REG_ECC_M3 … #define ONENAND_REG_ECC_S3 … /* * Device ID Register F001h (R) */ #define DEVICE_IS_FLEXONENAND … #define FLEXONENAND_PI_MASK … #define FLEXONENAND_PI_UNLOCK_SHIFT … #define ONENAND_DEVICE_DENSITY_MASK … #define ONENAND_DEVICE_DENSITY_SHIFT … #define ONENAND_DEVICE_IS_DDP … #define ONENAND_DEVICE_IS_DEMUX … #define ONENAND_DEVICE_VCC_MASK … #define ONENAND_DEVICE_DENSITY_512Mb … #define ONENAND_DEVICE_DENSITY_1Gb … #define ONENAND_DEVICE_DENSITY_2Gb … #define ONENAND_DEVICE_DENSITY_4Gb … #define ONENAND_DEVICE_DENSITY_8Gb … /* * Version ID Register F002h (R) */ #define ONENAND_VERSION_PROCESS_SHIFT … /* * Technology Register F006h (R) */ #define ONENAND_TECHNOLOGY_IS_MLC … /* * Start Address 1 F100h (R/W) & Start Address 2 F101h (R/W) */ #define ONENAND_DDP_SHIFT … #define ONENAND_DDP_CHIP0 … #define ONENAND_DDP_CHIP1 … /* * Start Address 8 F107h (R/W) */ /* Note: It's actually 0x3f in case of SLC */ #define ONENAND_FPA_MASK … #define ONENAND_FPA_SHIFT … #define ONENAND_FSA_MASK … /* * Start Buffer Register F200h (R/W) */ #define ONENAND_BSA_MASK … #define ONENAND_BSA_SHIFT … #define ONENAND_BSA_BOOTRAM … #define ONENAND_BSA_DATARAM0 … #define ONENAND_BSA_DATARAM1 … /* Note: It's actually 0x03 in case of SLC */ #define ONENAND_BSC_MASK … /* * Command Register F220h (R/W) */ #define ONENAND_CMD_READ … #define ONENAND_CMD_READOOB … #define ONENAND_CMD_PROG … #define ONENAND_CMD_PROGOOB … #define ONENAND_CMD_2X_PROG … #define ONENAND_CMD_2X_CACHE_PROG … #define ONENAND_CMD_UNLOCK … #define ONENAND_CMD_LOCK … #define ONENAND_CMD_LOCK_TIGHT … #define ONENAND_CMD_UNLOCK_ALL … #define ONENAND_CMD_ERASE … #define ONENAND_CMD_MULTIBLOCK_ERASE … #define ONENAND_CMD_ERASE_VERIFY … #define ONENAND_CMD_RESET … #define ONENAND_CMD_OTP_ACCESS … #define ONENAND_CMD_READID … #define FLEXONENAND_CMD_PI_UPDATE … #define FLEXONENAND_CMD_PI_ACCESS … #define FLEXONENAND_CMD_RECOVER_LSB … /* NOTE: Those are not *REAL* commands */ #define ONENAND_CMD_BUFFERRAM … #define FLEXONENAND_CMD_READ_PI … /* * System Configuration 1 Register F221h (R, R/W) */ #define ONENAND_SYS_CFG1_SYNC_READ … #define ONENAND_SYS_CFG1_BRL_7 … #define ONENAND_SYS_CFG1_BRL_6 … #define ONENAND_SYS_CFG1_BRL_5 … #define ONENAND_SYS_CFG1_BRL_4 … #define ONENAND_SYS_CFG1_BRL_3 … #define ONENAND_SYS_CFG1_BRL_10 … #define ONENAND_SYS_CFG1_BRL_9 … #define ONENAND_SYS_CFG1_BRL_8 … #define ONENAND_SYS_CFG1_BRL_SHIFT … #define ONENAND_SYS_CFG1_BL_32 … #define ONENAND_SYS_CFG1_BL_16 … #define ONENAND_SYS_CFG1_BL_8 … #define ONENAND_SYS_CFG1_BL_4 … #define ONENAND_SYS_CFG1_BL_CONT … #define ONENAND_SYS_CFG1_BL_SHIFT … #define ONENAND_SYS_CFG1_NO_ECC … #define ONENAND_SYS_CFG1_RDY … #define ONENAND_SYS_CFG1_INT … #define ONENAND_SYS_CFG1_IOBE … #define ONENAND_SYS_CFG1_RDY_CONF … #define ONENAND_SYS_CFG1_VHF … #define ONENAND_SYS_CFG1_HF … #define ONENAND_SYS_CFG1_SYNC_WRITE … /* * Controller Status Register F240h (R) */ #define ONENAND_CTRL_ONGO … #define ONENAND_CTRL_LOCK … #define ONENAND_CTRL_LOAD … #define ONENAND_CTRL_PROGRAM … #define ONENAND_CTRL_ERASE … #define ONENAND_CTRL_ERROR … #define ONENAND_CTRL_RSTB … #define ONENAND_CTRL_OTP_L … #define ONENAND_CTRL_OTP_BL … /* * Interrupt Status Register F241h (R) */ #define ONENAND_INT_MASTER … #define ONENAND_INT_READ … #define ONENAND_INT_WRITE … #define ONENAND_INT_ERASE … #define ONENAND_INT_RESET … #define ONENAND_INT_CLEAR … /* * NAND Flash Write Protection Status Register F24Eh (R) */ #define ONENAND_WP_US … #define ONENAND_WP_LS … #define ONENAND_WP_LTS … /* * ECC Status Reigser FF00h (R) */ #define ONENAND_ECC_1BIT … #define ONENAND_ECC_1BIT_ALL … #define ONENAND_ECC_2BIT … #define ONENAND_ECC_2BIT_ALL … #define FLEXONENAND_UNCORRECTABLE_ERROR … #define ONENAND_ECC_3BIT … #define ONENAND_ECC_4BIT … #define ONENAND_ECC_4BIT_UNCORRECTABLE … /* * One-Time Programmable (OTP) */ #define FLEXONENAND_OTP_LOCK_OFFSET … #define ONENAND_OTP_LOCK_OFFSET … #endif /* __ONENAND_REG_H */
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