/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Freescale GPMI NAND Flash Driver * * Copyright 2008-2011 Freescale Semiconductor, Inc. * Copyright 2008 Embedded Alley Solutions, Inc. */ #ifndef __GPMI_NAND_GPMI_REGS_H #define __GPMI_NAND_GPMI_REGS_H #define HW_GPMI_CTRL0 … #define HW_GPMI_CTRL0_SET … #define HW_GPMI_CTRL0_CLR … #define HW_GPMI_CTRL0_TOG … #define BP_GPMI_CTRL0_COMMAND_MODE … #define BM_GPMI_CTRL0_COMMAND_MODE … #define BF_GPMI_CTRL0_COMMAND_MODE(v) … #define BV_GPMI_CTRL0_COMMAND_MODE__WRITE … #define BV_GPMI_CTRL0_COMMAND_MODE__READ … #define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE … #define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY … #define BM_GPMI_CTRL0_WORD_LENGTH … #define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT … #define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT … /* * Difference in LOCK_CS between imx23 and imx28 : * This bit may impact the _POWER_ consumption. So some chips * do not set it. */ #define MX23_BP_GPMI_CTRL0_LOCK_CS … #define MX28_BP_GPMI_CTRL0_LOCK_CS … #define LOCK_CS_ENABLE … #define BF_GPMI_CTRL0_LOCK_CS(v, x) … /* Difference in CS between imx23 and imx28 */ #define BP_GPMI_CTRL0_CS … #define MX23_BM_GPMI_CTRL0_CS … #define MX28_BM_GPMI_CTRL0_CS … #define BF_GPMI_CTRL0_CS(v, x) … #define BP_GPMI_CTRL0_ADDRESS … #define BM_GPMI_CTRL0_ADDRESS … #define BF_GPMI_CTRL0_ADDRESS(v) … #define BV_GPMI_CTRL0_ADDRESS__NAND_DATA … #define BV_GPMI_CTRL0_ADDRESS__NAND_CLE … #define BV_GPMI_CTRL0_ADDRESS__NAND_ALE … #define BM_GPMI_CTRL0_ADDRESS_INCREMENT … #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED … #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED … #define BP_GPMI_CTRL0_XFER_COUNT … #define BM_GPMI_CTRL0_XFER_COUNT … #define BF_GPMI_CTRL0_XFER_COUNT(v) … #define HW_GPMI_COMPARE … #define HW_GPMI_ECCCTRL … #define HW_GPMI_ECCCTRL_SET … #define HW_GPMI_ECCCTRL_CLR … #define HW_GPMI_ECCCTRL_TOG … #define BP_GPMI_ECCCTRL_ECC_CMD … #define BM_GPMI_ECCCTRL_ECC_CMD … #define BF_GPMI_ECCCTRL_ECC_CMD(v) … #define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE … #define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE … #define BM_GPMI_ECCCTRL_ENABLE_ECC … #define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE … #define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE … #define BP_GPMI_ECCCTRL_BUFFER_MASK … #define BM_GPMI_ECCCTRL_BUFFER_MASK … #define BF_GPMI_ECCCTRL_BUFFER_MASK(v) … #define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY … #define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE … #define HW_GPMI_ECCCOUNT … #define HW_GPMI_PAYLOAD … #define HW_GPMI_AUXILIARY … #define HW_GPMI_CTRL1 … #define HW_GPMI_CTRL1_SET … #define HW_GPMI_CTRL1_CLR … #define HW_GPMI_CTRL1_TOG … #define BP_GPMI_CTRL1_DECOUPLE_CS … #define BM_GPMI_CTRL1_DECOUPLE_CS … #define BP_GPMI_CTRL1_WRN_DLY_SEL … #define BM_GPMI_CTRL1_WRN_DLY_SEL … #define BF_GPMI_CTRL1_WRN_DLY_SEL(v) … #define BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS … #define BV_GPMI_CTRL1_WRN_DLY_SEL_6_TO_10NS … #define BV_GPMI_CTRL1_WRN_DLY_SEL_7_TO_12NS … #define BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY … #define BM_GPMI_CTRL1_GANGED_RDYBUSY … #define BM_GPMI_CTRL1_BCH_MODE … #define BP_GPMI_CTRL1_DLL_ENABLE … #define BM_GPMI_CTRL1_DLL_ENABLE … #define BP_GPMI_CTRL1_HALF_PERIOD … #define BM_GPMI_CTRL1_HALF_PERIOD … #define BP_GPMI_CTRL1_RDN_DELAY … #define BM_GPMI_CTRL1_RDN_DELAY … #define BF_GPMI_CTRL1_RDN_DELAY(v) … #define BM_GPMI_CTRL1_DEV_RESET … #define BV_GPMI_CTRL1_DEV_RESET__ENABLED … #define BV_GPMI_CTRL1_DEV_RESET__DISABLED … #define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY … #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW … #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH … #define BM_GPMI_CTRL1_CAMERA_MODE … #define BV_GPMI_CTRL1_GPMI_MODE__NAND … #define BV_GPMI_CTRL1_GPMI_MODE__ATA … #define BM_GPMI_CTRL1_GPMI_MODE … #define BM_GPMI_CTRL1_CLEAR_MASK … #define HW_GPMI_TIMING0 … #define BP_GPMI_TIMING0_ADDRESS_SETUP … #define BM_GPMI_TIMING0_ADDRESS_SETUP … #define BF_GPMI_TIMING0_ADDRESS_SETUP(v) … #define BP_GPMI_TIMING0_DATA_HOLD … #define BM_GPMI_TIMING0_DATA_HOLD … #define BF_GPMI_TIMING0_DATA_HOLD(v) … #define BP_GPMI_TIMING0_DATA_SETUP … #define BM_GPMI_TIMING0_DATA_SETUP … #define BF_GPMI_TIMING0_DATA_SETUP(v) … #define HW_GPMI_TIMING1 … #define BP_GPMI_TIMING1_BUSY_TIMEOUT … #define BM_GPMI_TIMING1_BUSY_TIMEOUT … #define BF_GPMI_TIMING1_BUSY_TIMEOUT(v) … #define HW_GPMI_TIMING2 … #define HW_GPMI_DATA … /* MX28 uses this to detect READY. */ #define HW_GPMI_STAT … #define MX28_BP_GPMI_STAT_READY_BUSY … #define MX28_BM_GPMI_STAT_READY_BUSY … #define MX28_BF_GPMI_STAT_READY_BUSY(v) … /* MX23 uses this to detect READY. */ #define HW_GPMI_DEBUG … #define MX23_BP_GPMI_DEBUG_READY0 … #define MX23_BM_GPMI_DEBUG_READY0 … #endif
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