// SPDX-License-Identifier: GPL-2.0+ /* * Freescale GPMI NAND Flash Driver * * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. * Copyright (C) 2008 Embedded Alley Solutions, Inc. */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/sched/task_stack.h> #include <linux/interrupt.h> #include <linux/module.h> #include <linux/mtd/partitions.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/dma/mxs-dma.h> #include "gpmi-nand.h" #include "gpmi-regs.h" #include "bch-regs.h" /* Resource names for the GPMI NAND driver. */ #define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME … #define GPMI_NAND_BCH_REGS_ADDR_RES_NAME … #define GPMI_NAND_BCH_INTERRUPT_RES_NAME … /* Converts time to clock cycles */ #define TO_CYCLES(duration, period) … #define MXS_SET_ADDR … #define MXS_CLR_ADDR … /* * Clear the bit and poll it cleared. This is usually called with * a reset address and mask being either SFTRST(bit 31) or CLKGATE * (bit 30). */ static int clear_poll_bit(void __iomem *addr, u32 mask) { … } #define MODULE_CLKGATE … #define MODULE_SFTRST … /* * The current mxs_reset_block() will do two things: * [1] enable the module. * [2] reset the module. * * In most of the cases, it's ok. * But in MX23, there is a hardware bug in the BCH block (see erratum #2847). * If you try to soft reset the BCH block, it becomes unusable until * the next hard reset. This case occurs in the NAND boot mode. When the board * boots by NAND, the ROM of the chip will initialize the BCH blocks itself. * So If the driver tries to reset the BCH again, the BCH will not work anymore. * You will see a DMA timeout in this case. The bug has been fixed * in the following chips, such as MX28. * * To avoid this bug, just add a new parameter `just_enable` for * the mxs_reset_block(), and rewrite it here. */ static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable) { … } static int __gpmi_enable_clk(struct gpmi_nand_data *this, bool v) { … } static int gpmi_init(struct gpmi_nand_data *this) { … } /* This function is very useful. It is called only when the bug occur. */ static void gpmi_dump_info(struct gpmi_nand_data *this) { … } static bool gpmi_check_ecc(struct gpmi_nand_data *this) { … } /* check if bbm locates in data chunk rather than ecc chunk */ static bool bbm_in_data_chunk(struct gpmi_nand_data *this, unsigned int *chunk_num) { … } /* * If we can get the ECC information from the nand chip, we do not * need to calculate them ourselves. * * We may have available oob space in this case. */ static int set_geometry_by_ecc_info(struct gpmi_nand_data *this, unsigned int ecc_strength, unsigned int ecc_step) { … } /* * Calculate the ECC strength by hand: * E : The ECC strength. * G : the length of Galois Field. * N : The chunk count of per page. * O : the oobsize of the NAND chip. * M : the metasize of per page. * * The formula is : * E * G * N * ------------ <= (O - M) * 8 * * So, we get E by: * (O - M) * 8 * E <= ------------- * G * N */ static inline int get_ecc_strength(struct gpmi_nand_data *this) { … } static int set_geometry_for_large_oob(struct gpmi_nand_data *this) { … } static int legacy_set_geometry(struct gpmi_nand_data *this) { … } static int common_nfc_set_geometry(struct gpmi_nand_data *this) { … } /* Configures the geometry for BCH. */ static int bch_set_geometry(struct gpmi_nand_data *this) { … } /* * <1> Firstly, we should know what's the GPMI-clock means. * The GPMI-clock is the internal clock in the gpmi nand controller. * If you set 100MHz to gpmi nand controller, the GPMI-clock's period * is 10ns. Mark the GPMI-clock's period as GPMI-clock-period. * * <2> Secondly, we should know what's the frequency on the nand chip pins. * The frequency on the nand chip pins is derived from the GPMI-clock. * We can get it from the following equation: * * F = G / (DS + DH) * * F : the frequency on the nand chip pins. * G : the GPMI clock, such as 100MHz. * DS : GPMI_HW_GPMI_TIMING0:DATA_SETUP * DH : GPMI_HW_GPMI_TIMING0:DATA_HOLD * * <3> Thirdly, when the frequency on the nand chip pins is above 33MHz, * the nand EDO(extended Data Out) timing could be applied. * The GPMI implements a feedback read strobe to sample the read data. * The feedback read strobe can be delayed to support the nand EDO timing * where the read strobe may deasserts before the read data is valid, and * read data is valid for some time after read strobe. * * The following figure illustrates some aspects of a NAND Flash read: * * |<---tREA---->| * | | * | | | * |<--tRP-->| | * | | | * __ ___|__________________________________ * RDN \________/ | * | * /---------\ * Read Data --------------< >--------- * \---------/ * | | * |<-D->| * FeedbackRDN ________ ____________ * \___________/ * * D stands for delay, set in the HW_GPMI_CTRL1:RDN_DELAY. * * * <4> Now, we begin to describe how to compute the right RDN_DELAY. * * 4.1) From the aspect of the nand chip pins: * Delay = (tREA + C - tRP) {1} * * tREA : the maximum read access time. * C : a constant to adjust the delay. default is 4000ps. * tRP : the read pulse width, which is exactly: * tRP = (GPMI-clock-period) * DATA_SETUP * * 4.2) From the aspect of the GPMI nand controller: * Delay = RDN_DELAY * 0.125 * RP {2} * * RP : the DLL reference period. * if (GPMI-clock-period > DLL_THRETHOLD) * RP = GPMI-clock-period / 2; * else * RP = GPMI-clock-period; * * Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period * is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD * is 16000ps, but in mx6q, we use 12000ps. * * 4.3) since {1} equals {2}, we get: * * (tREA + 4000 - tRP) * 8 * RDN_DELAY = ----------------------- {3} * RP */ static int gpmi_nfc_compute_timings(struct gpmi_nand_data *this, const struct nand_sdr_timings *sdr) { … } static int gpmi_nfc_apply_timings(struct gpmi_nand_data *this) { … } static int gpmi_setup_interface(struct nand_chip *chip, int chipnr, const struct nand_interface_config *conf) { … } /* Clears a BCH interrupt. */ static void gpmi_clear_bch(struct gpmi_nand_data *this) { … } static struct dma_chan *get_dma_chan(struct gpmi_nand_data *this) { … } /* This will be called after the DMA operation is finished. */ static void dma_irq_callback(void *param) { … } static irqreturn_t bch_irq(int irq, void *cookie) { … } static int gpmi_raw_len_to_len(struct gpmi_nand_data *this, int raw_len) { … } /* Can we use the upper's buffer directly for DMA? */ static bool prepare_data_dma(struct gpmi_nand_data *this, const void *buf, int raw_len, struct scatterlist *sgl, enum dma_data_direction dr) { … } /* add our owner bbt descriptor */ static uint8_t scan_ff_pattern[] = …; static struct nand_bbt_descr gpmi_bbt_descr = …; /* * We may change the layout if we can get the ECC info from the datasheet, * else we will use all the (page + OOB). */ static int gpmi_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *oobregion) { … } static int gpmi_ooblayout_free(struct mtd_info *mtd, int section, struct mtd_oob_region *oobregion) { … } static const char * const gpmi_clks_for_mx2x[] = …; static const struct mtd_ooblayout_ops gpmi_ooblayout_ops = …; static const struct gpmi_devdata gpmi_devdata_imx23 = …; static const struct gpmi_devdata gpmi_devdata_imx28 = …; static const char * const gpmi_clks_for_mx6[] = …; static const struct gpmi_devdata gpmi_devdata_imx6q = …; static const struct gpmi_devdata gpmi_devdata_imx6sx = …; static const char * const gpmi_clks_for_mx7d[] = …; static const struct gpmi_devdata gpmi_devdata_imx7d = …; static const char *gpmi_clks_for_mx8qxp[GPMI_CLK_MAX] = …; static const struct gpmi_devdata gpmi_devdata_imx8qxp = …; static int acquire_register_block(struct gpmi_nand_data *this, const char *res_name) { … } static int acquire_bch_irq(struct gpmi_nand_data *this, irq_handler_t irq_h) { … } static void release_dma_channels(struct gpmi_nand_data *this) { … } static int acquire_dma_channels(struct gpmi_nand_data *this) { … } static int gpmi_get_clks(struct gpmi_nand_data *this) { … } static int acquire_resources(struct gpmi_nand_data *this) { … } static void release_resources(struct gpmi_nand_data *this) { … } static void gpmi_free_dma_buffer(struct gpmi_nand_data *this) { … } /* Allocate the DMA buffers */ static int gpmi_alloc_dma_buffer(struct gpmi_nand_data *this) { … } /* * Handles block mark swapping. * It can be called in swapping the block mark, or swapping it back, * because the operations are the same. */ static void block_mark_swapping(struct gpmi_nand_data *this, void *payload, void *auxiliary) { … } static int gpmi_count_bitflips(struct nand_chip *chip, void *buf, int first, int last, int meta) { … } static void gpmi_bch_layout_std(struct gpmi_nand_data *this) { … } static int gpmi_ecc_read_page(struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { … } /* Fake a virtual small page for the subpage read */ static int gpmi_ecc_read_subpage(struct nand_chip *chip, uint32_t offs, uint32_t len, uint8_t *buf, int page) { … } static int gpmi_ecc_write_page(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page) { … } /* * There are several places in this driver where we have to handle the OOB and * block marks. This is the function where things are the most complicated, so * this is where we try to explain it all. All the other places refer back to * here. * * These are the rules, in order of decreasing importance: * * 1) Nothing the caller does can be allowed to imperil the block mark. * * 2) In read operations, the first byte of the OOB we return must reflect the * true state of the block mark, no matter where that block mark appears in * the physical page. * * 3) ECC-based read operations return an OOB full of set bits (since we never * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads * return). * * 4) "Raw" read operations return a direct view of the physical bytes in the * page, using the conventional definition of which bytes are data and which * are OOB. This gives the caller a way to see the actual, physical bytes * in the page, without the distortions applied by our ECC engine. * * * What we do for this specific read operation depends on two questions: * * 1) Are we doing a "raw" read, or an ECC-based read? * * 2) Are we using block mark swapping or transcription? * * There are four cases, illustrated by the following Karnaugh map: * * | Raw | ECC-based | * -------------+-------------------------+-------------------------+ * | Read the conventional | | * | OOB at the end of the | | * Swapping | page and return it. It | | * | contains exactly what | | * | we want. | Read the block mark and | * -------------+-------------------------+ return it in a buffer | * | Read the conventional | full of set bits. | * | OOB at the end of the | | * | page and also the block | | * Transcribing | mark in the metadata. | | * | Copy the block mark | | * | into the first byte of | | * | the OOB. | | * -------------+-------------------------+-------------------------+ * * Note that we break rule #4 in the Transcribing/Raw case because we're not * giving an accurate view of the actual, physical bytes in the page (we're * overwriting the block mark). That's OK because it's more important to follow * rule #2. * * It turns out that knowing whether we want an "ECC-based" or "raw" read is not * easy. When reading a page, for example, the NAND Flash MTD code calls our * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an * ECC-based or raw view of the page is implicit in which function it calls * (there is a similar pair of ECC-based/raw functions for writing). */ static int gpmi_ecc_read_oob(struct nand_chip *chip, int page) { … } static int gpmi_ecc_write_oob(struct nand_chip *chip, int page) { … } /* * This function reads a NAND page without involving the ECC engine (no HW * ECC correction). * The tricky part in the GPMI/BCH controller is that it stores ECC bits * inline (interleaved with payload DATA), and do not align data chunk on * byte boundaries. * We thus need to take care moving the payload data and ECC bits stored in the * page into the provided buffers, which is why we're using nand_extract_bits(). * * See set_geometry_by_ecc_info inline comments to have a full description * of the layout used by the GPMI controller. */ static int gpmi_ecc_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { … } /* * This function writes a NAND page without involving the ECC engine (no HW * ECC generation). * The tricky part in the GPMI/BCH controller is that it stores ECC bits * inline (interleaved with payload DATA), and do not align data chunk on * byte boundaries. * We thus need to take care moving the OOB area at the right place in the * final page, which is why we're using nand_extract_bits(). * * See set_geometry_by_ecc_info inline comments to have a full description * of the layout used by the GPMI controller. */ static int gpmi_ecc_write_page_raw(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page) { … } static int gpmi_ecc_read_oob_raw(struct nand_chip *chip, int page) { … } static int gpmi_ecc_write_oob_raw(struct nand_chip *chip, int page) { … } static int gpmi_block_markbad(struct nand_chip *chip, loff_t ofs) { … } static int nand_boot_set_geometry(struct gpmi_nand_data *this) { … } static const char *fingerprint = …; static int mx23_check_transcription_stamp(struct gpmi_nand_data *this) { … } /* Writes a transcription stamp. */ static int mx23_write_transcription_stamp(struct gpmi_nand_data *this) { … } static int mx23_boot_init(struct gpmi_nand_data *this) { … } static int nand_boot_init(struct gpmi_nand_data *this) { … } static int gpmi_set_geometry(struct gpmi_nand_data *this) { … } static int gpmi_init_last(struct gpmi_nand_data *this) { … } static int gpmi_nand_attach_chip(struct nand_chip *chip) { … } static struct gpmi_transfer *get_next_transfer(struct gpmi_nand_data *this) { … } static struct dma_async_tx_descriptor *gpmi_chain_command( struct gpmi_nand_data *this, u8 cmd, const u8 *addr, int naddr) { … } static struct dma_async_tx_descriptor *gpmi_chain_wait_ready( struct gpmi_nand_data *this) { … } static struct dma_async_tx_descriptor *gpmi_chain_data_read( struct gpmi_nand_data *this, void *buf, int raw_len, bool *direct) { … } static struct dma_async_tx_descriptor *gpmi_chain_data_write( struct gpmi_nand_data *this, const void *buf, int raw_len) { … } static int gpmi_nfc_exec_op(struct nand_chip *chip, const struct nand_operation *op, bool check_only) { … } static const struct nand_controller_ops gpmi_nand_controller_ops = …; static int gpmi_nand_init(struct gpmi_nand_data *this) { … } static const struct of_device_id gpmi_nand_id_table[] = …; MODULE_DEVICE_TABLE(of, gpmi_nand_id_table); static int gpmi_nand_probe(struct platform_device *pdev) { … } static void gpmi_nand_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int gpmi_pm_suspend(struct device *dev) { … } static int gpmi_pm_resume(struct device *dev) { … } #endif /* CONFIG_PM_SLEEP */ static int __maybe_unused gpmi_runtime_suspend(struct device *dev) { … } static int __maybe_unused gpmi_runtime_resume(struct device *dev) { … } static const struct dev_pm_ops gpmi_pm_ops = …; static struct platform_driver gpmi_nand_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;