/* SPDX-License-Identifier: GPL-2.0 */ /* * NAND Flash Controller Device Driver * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers. */ #ifndef __DENALI_H__ #define __DENALI_H__ #include <linux/bits.h> #include <linux/completion.h> #include <linux/list.h> #include <linux/mtd/rawnand.h> #include <linux/spinlock_types.h> #include <linux/types.h> #define DEVICE_RESET … #define DEVICE_RESET__BANK(bank) … #define TRANSFER_SPARE_REG … #define TRANSFER_SPARE_REG__FLAG … #define LOAD_WAIT_CNT … #define LOAD_WAIT_CNT__VALUE … #define PROGRAM_WAIT_CNT … #define PROGRAM_WAIT_CNT__VALUE … #define ERASE_WAIT_CNT … #define ERASE_WAIT_CNT__VALUE … #define INT_MON_CYCCNT … #define INT_MON_CYCCNT__VALUE … #define RB_PIN_ENABLED … #define RB_PIN_ENABLED__BANK(bank) … #define MULTIPLANE_OPERATION … #define MULTIPLANE_OPERATION__FLAG … #define MULTIPLANE_READ_ENABLE … #define MULTIPLANE_READ_ENABLE__FLAG … #define COPYBACK_DISABLE … #define COPYBACK_DISABLE__FLAG … #define CACHE_WRITE_ENABLE … #define CACHE_WRITE_ENABLE__FLAG … #define CACHE_READ_ENABLE … #define CACHE_READ_ENABLE__FLAG … #define PREFETCH_MODE … #define PREFETCH_MODE__PREFETCH_EN … #define PREFETCH_MODE__PREFETCH_BURST_LENGTH … #define CHIP_ENABLE_DONT_CARE … #define CHIP_EN_DONT_CARE__FLAG … #define ECC_ENABLE … #define ECC_ENABLE__FLAG … #define GLOBAL_INT_ENABLE … #define GLOBAL_INT_EN_FLAG … #define TWHR2_AND_WE_2_RE … #define TWHR2_AND_WE_2_RE__WE_2_RE … #define TWHR2_AND_WE_2_RE__TWHR2 … #define TCWAW_AND_ADDR_2_DATA … /* The width of ADDR_2_DATA is 6 bit for old IP, 7 bit for new IP */ #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA … #define TCWAW_AND_ADDR_2_DATA__TCWAW … #define RE_2_WE … #define RE_2_WE__VALUE … #define ACC_CLKS … #define ACC_CLKS__VALUE … #define NUMBER_OF_PLANES … #define NUMBER_OF_PLANES__VALUE … #define PAGES_PER_BLOCK … #define PAGES_PER_BLOCK__VALUE … #define DEVICE_WIDTH … #define DEVICE_WIDTH__VALUE … #define DEVICE_MAIN_AREA_SIZE … #define DEVICE_MAIN_AREA_SIZE__VALUE … #define DEVICE_SPARE_AREA_SIZE … #define DEVICE_SPARE_AREA_SIZE__VALUE … #define TWO_ROW_ADDR_CYCLES … #define TWO_ROW_ADDR_CYCLES__FLAG … #define MULTIPLANE_ADDR_RESTRICT … #define MULTIPLANE_ADDR_RESTRICT__FLAG … #define ECC_CORRECTION … #define ECC_CORRECTION__VALUE … #define ECC_CORRECTION__ERASE_THRESHOLD … #define READ_MODE … #define READ_MODE__VALUE … #define WRITE_MODE … #define WRITE_MODE__VALUE … #define COPYBACK_MODE … #define COPYBACK_MODE__VALUE … #define RDWR_EN_LO_CNT … #define RDWR_EN_LO_CNT__VALUE … #define RDWR_EN_HI_CNT … #define RDWR_EN_HI_CNT__VALUE … #define MAX_RD_DELAY … #define MAX_RD_DELAY__VALUE … #define CS_SETUP_CNT … #define CS_SETUP_CNT__VALUE … #define CS_SETUP_CNT__TWB … #define SPARE_AREA_SKIP_BYTES … #define SPARE_AREA_SKIP_BYTES__VALUE … #define SPARE_AREA_MARKER … #define SPARE_AREA_MARKER__VALUE … #define DEVICES_CONNECTED … #define DEVICES_CONNECTED__VALUE … #define DIE_MASK … #define DIE_MASK__VALUE … #define FIRST_BLOCK_OF_NEXT_PLANE … #define FIRST_BLOCK_OF_NEXT_PLANE__VALUE … #define WRITE_PROTECT … #define WRITE_PROTECT__FLAG … #define RE_2_RE … #define RE_2_RE__VALUE … #define MANUFACTURER_ID … #define MANUFACTURER_ID__VALUE … #define DEVICE_ID … #define DEVICE_ID__VALUE … #define DEVICE_PARAM_0 … #define DEVICE_PARAM_0__VALUE … #define DEVICE_PARAM_1 … #define DEVICE_PARAM_1__VALUE … #define DEVICE_PARAM_2 … #define DEVICE_PARAM_2__VALUE … #define LOGICAL_PAGE_DATA_SIZE … #define LOGICAL_PAGE_DATA_SIZE__VALUE … #define LOGICAL_PAGE_SPARE_SIZE … #define LOGICAL_PAGE_SPARE_SIZE__VALUE … #define REVISION … #define REVISION__VALUE … #define ONFI_DEVICE_FEATURES … #define ONFI_DEVICE_FEATURES__VALUE … #define ONFI_OPTIONAL_COMMANDS … #define ONFI_OPTIONAL_COMMANDS__VALUE … #define ONFI_TIMING_MODE … #define ONFI_TIMING_MODE__VALUE … #define ONFI_PGM_CACHE_TIMING_MODE … #define ONFI_PGM_CACHE_TIMING_MODE__VALUE … #define ONFI_DEVICE_NO_OF_LUNS … #define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS … #define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE … #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L … #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE … #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U … #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE … #define FEATURES … #define FEATURES__N_BANKS … #define FEATURES__ECC_MAX_ERR … #define FEATURES__DMA … #define FEATURES__CMD_DMA … #define FEATURES__PARTITION … #define FEATURES__XDMA_SIDEBAND … #define FEATURES__GPREG … #define FEATURES__INDEX_ADDR … #define TRANSFER_MODE … #define TRANSFER_MODE__VALUE … #define INTR_STATUS(bank) … #define INTR_EN(bank) … /* bit[1:0] is used differently depending on IP version */ #define INTR__ECC_UNCOR_ERR … #define INTR__ECC_TRANSACTION_DONE … #define INTR__ECC_ERR … #define INTR__DMA_CMD_COMP … #define INTR__TIME_OUT … #define INTR__PROGRAM_FAIL … #define INTR__ERASE_FAIL … #define INTR__LOAD_COMP … #define INTR__PROGRAM_COMP … #define INTR__ERASE_COMP … #define INTR__PIPE_CPYBCK_CMD_COMP … #define INTR__LOCKED_BLK … #define INTR__UNSUP_CMD … #define INTR__INT_ACT … #define INTR__RST_COMP … #define INTR__PIPE_CMD_ERR … #define INTR__PAGE_XFER_INC … #define INTR__ERASED_PAGE … #define PAGE_CNT(bank) … #define ERR_PAGE_ADDR(bank) … #define ERR_BLOCK_ADDR(bank) … #define ECC_THRESHOLD … #define ECC_THRESHOLD__VALUE … #define ECC_ERROR_BLOCK_ADDRESS … #define ECC_ERROR_BLOCK_ADDRESS__VALUE … #define ECC_ERROR_PAGE_ADDRESS … #define ECC_ERROR_PAGE_ADDRESS__VALUE … #define ECC_ERROR_PAGE_ADDRESS__BANK … #define ECC_ERROR_ADDRESS … #define ECC_ERROR_ADDRESS__OFFSET … #define ECC_ERROR_ADDRESS__SECTOR … #define ERR_CORRECTION_INFO … #define ERR_CORRECTION_INFO__BYTE … #define ERR_CORRECTION_INFO__DEVICE … #define ERR_CORRECTION_INFO__UNCOR … #define ERR_CORRECTION_INFO__LAST_ERR … #define ECC_COR_INFO(bank) … #define ECC_COR_INFO__SHIFT(bank) … #define ECC_COR_INFO__MAX_ERRORS … #define ECC_COR_INFO__UNCOR_ERR … #define CFG_DATA_BLOCK_SIZE … #define CFG_LAST_DATA_BLOCK_SIZE … #define CFG_NUM_DATA_BLOCKS … #define CFG_META_DATA_SIZE … #define DMA_ENABLE … #define DMA_ENABLE__FLAG … #define IGNORE_ECC_DONE … #define IGNORE_ECC_DONE__FLAG … #define DMA_INTR … #define DMA_INTR_EN … #define DMA_INTR__TARGET_ERROR … #define DMA_INTR__DESC_COMP_CHANNEL0 … #define DMA_INTR__DESC_COMP_CHANNEL1 … #define DMA_INTR__DESC_COMP_CHANNEL2 … #define DMA_INTR__DESC_COMP_CHANNEL3 … #define DMA_INTR__MEMCOPY_DESC_COMP … #define TARGET_ERR_ADDR_LO … #define TARGET_ERR_ADDR_LO__VALUE … #define TARGET_ERR_ADDR_HI … #define TARGET_ERR_ADDR_HI__VALUE … #define CHNL_ACTIVE … #define CHNL_ACTIVE__CHANNEL0 … #define CHNL_ACTIVE__CHANNEL1 … #define CHNL_ACTIVE__CHANNEL2 … #define CHNL_ACTIVE__CHANNEL3 … /** * struct denali_chip_sel - per-CS data of Denali NAND * * @bank: bank id of the controller this CS is connected to * @hwhr2_and_we_2_re: value of timing register HWHR2_AND_WE_2_RE * @tcwaw_and_addr_2_data: value of timing register TCWAW_AND_ADDR_2_DATA * @re_2_we: value of timing register RE_2_WE * @acc_clks: value of timing register ACC_CLKS * @rdwr_en_lo_cnt: value of timing register RDWR_EN_LO_CNT * @rdwr_en_hi_cnt: value of timing register RDWR_EN_HI_CNT * @cs_setup_cnt: value of timing register CS_SETUP_CNT * @re_2_re: value of timing register RE_2_RE */ struct denali_chip_sel { … }; /** * struct denali_chip - per-chip data of Denali NAND * * @chip: base NAND chip structure * @node: node to be used to associate this chip with the controller * @nsels: the number of CS lines of this chip * @sels: the array of per-cs data */ struct denali_chip { … }; /** * struct denali_controller - Denali NAND controller data * * @controller: base NAND controller structure * @dev: device * @chips: the list of chips attached to this controller * @clk_rate: frequency of core clock * @clk_x_rate: frequency of bus interface clock * @reg: base of Register Interface * @host: base of Host Data/Command interface * @complete: completion used to wait for interrupts * @irq: interrupt number * @irq_mask: interrupt bits the controller is waiting for * @irq_status: interrupt bits of events that have happened * @irq_lock: lock to protect @irq_mask and @irq_status * @dma_avail: set if DMA engine is available * @devs_per_cs: number of devices connected in parallel * @oob_skip_bytes: number of bytes in OOB skipped by the ECC engine * @active_bank: active bank id * @nbanks: the number of banks supported by this controller * @revision: IP revision * @caps: controller capabilities that cannot be detected run-time * @ecc_caps: ECC engine capabilities * @host_read: callback for read access of Host Data/Command Interface * @host_write: callback for write access of Host Data/Command Interface * @setup_dma: callback for setup of the Data DMA */ struct denali_controller { … }; #define DENALI_CAP_HW_ECC_FIXUP … #define DENALI_CAP_DMA_64BIT … int denali_calc_ecc_bytes(int step_size, int strength); int denali_chip_init(struct denali_controller *denali, struct denali_chip *dchip); int denali_init(struct denali_controller *denali); void denali_remove(struct denali_controller *denali); #endif /* __DENALI_H__ */
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