/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * mach-davinci/nand.h * * Copyright © 2006 Texas Instruments. * * Ported to 2.6.23 Copyright © 2008 by * Sander Huijsen <[email protected]> * Troy Kisky <[email protected]> * Dirk Behme <[email protected]> * * -------------------------------------------------------------------------- */ #ifndef __ARCH_ARM_DAVINCI_NAND_H #define __ARCH_ARM_DAVINCI_NAND_H #include <linux/mtd/rawnand.h> #define NANDFCR_OFFSET … #define NANDFSR_OFFSET … #define NANDF1ECC_OFFSET … /* 4-bit ECC syndrome registers */ #define NAND_4BIT_ECC_LOAD_OFFSET … #define NAND_4BIT_ECC1_OFFSET … #define NAND_4BIT_ECC2_OFFSET … #define NAND_4BIT_ECC3_OFFSET … #define NAND_4BIT_ECC4_OFFSET … #define NAND_ERR_ADD1_OFFSET … #define NAND_ERR_ADD2_OFFSET … #define NAND_ERR_ERRVAL1_OFFSET … #define NAND_ERR_ERRVAL2_OFFSET … /* NOTE: boards don't need to use these address bits * for ALE/CLE unless they support booting from NAND. * They're used unless platform data overrides them. */ #define MASK_ALE … #define MASK_CLE … struct davinci_nand_pdata { … }; #endif /* __ARCH_ARM_DAVINCI_NAND_H */
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