/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Freescale Integrated Flash Controller * * Copyright 2011 Freescale Semiconductor, Inc * * Author: Dipen Dudhat <[email protected]> */ #ifndef __ASM_FSL_IFC_H #define __ASM_FSL_IFC_H #include <linux/compiler.h> #include <linux/types.h> #include <linux/io.h> #include <linux/of_platform.h> #include <linux/interrupt.h> /* * The actual number of banks implemented depends on the IFC version * - IFC version 1.0 implements 4 banks. * - IFC version 1.1 onward implements 8 banks. */ #define FSL_IFC_BANK_COUNT … #define FSL_IFC_VERSION_MASK … #define FSL_IFC_VERSION_1_0_0 … #define FSL_IFC_VERSION_1_1_0 … #define FSL_IFC_VERSION_2_0_0 … #define PGOFFSET_64K … #define PGOFFSET_4K … /* * CSPR - Chip Select Property Register */ #define CSPR_BA … #define CSPR_BA_SHIFT … #define CSPR_PORT_SIZE … #define CSPR_PORT_SIZE_SHIFT … /* Port Size 8 bit */ #define CSPR_PORT_SIZE_8 … /* Port Size 16 bit */ #define CSPR_PORT_SIZE_16 … /* Port Size 32 bit */ #define CSPR_PORT_SIZE_32 … /* Write Protect */ #define CSPR_WP … #define CSPR_WP_SHIFT … /* Machine Select */ #define CSPR_MSEL … #define CSPR_MSEL_SHIFT … /* NOR */ #define CSPR_MSEL_NOR … /* NAND */ #define CSPR_MSEL_NAND … /* GPCM */ #define CSPR_MSEL_GPCM … /* Bank Valid */ #define CSPR_V … #define CSPR_V_SHIFT … /* * Address Mask Register */ #define IFC_AMASK_MASK … #define IFC_AMASK_SHIFT … #define IFC_AMASK(n) … /* * Chip Select Option Register IFC_NAND Machine */ /* Enable ECC Encoder */ #define CSOR_NAND_ECC_ENC_EN … #define CSOR_NAND_ECC_MODE_MASK … /* 4 bit correction per 520 Byte sector */ #define CSOR_NAND_ECC_MODE_4 … /* 8 bit correction per 528 Byte sector */ #define CSOR_NAND_ECC_MODE_8 … /* Enable ECC Decoder */ #define CSOR_NAND_ECC_DEC_EN … /* Row Address Length */ #define CSOR_NAND_RAL_MASK … #define CSOR_NAND_RAL_SHIFT … #define CSOR_NAND_RAL_1 … #define CSOR_NAND_RAL_2 … #define CSOR_NAND_RAL_3 … #define CSOR_NAND_RAL_4 … /* Page Size 512b, 2k, 4k */ #define CSOR_NAND_PGS_MASK … #define CSOR_NAND_PGS_SHIFT … #define CSOR_NAND_PGS_512 … #define CSOR_NAND_PGS_2K … #define CSOR_NAND_PGS_4K … #define CSOR_NAND_PGS_8K … /* Spare region Size */ #define CSOR_NAND_SPRZ_MASK … #define CSOR_NAND_SPRZ_SHIFT … #define CSOR_NAND_SPRZ_16 … #define CSOR_NAND_SPRZ_64 … #define CSOR_NAND_SPRZ_128 … #define CSOR_NAND_SPRZ_210 … #define CSOR_NAND_SPRZ_218 … #define CSOR_NAND_SPRZ_224 … #define CSOR_NAND_SPRZ_CSOR_EXT … /* Pages Per Block */ #define CSOR_NAND_PB_MASK … #define CSOR_NAND_PB_SHIFT … #define CSOR_NAND_PB(n) … /* Time for Read Enable High to Output High Impedance */ #define CSOR_NAND_TRHZ_MASK … #define CSOR_NAND_TRHZ_SHIFT … #define CSOR_NAND_TRHZ_20 … #define CSOR_NAND_TRHZ_40 … #define CSOR_NAND_TRHZ_60 … #define CSOR_NAND_TRHZ_80 … #define CSOR_NAND_TRHZ_100 … /* Buffer control disable */ #define CSOR_NAND_BCTLD … /* * Chip Select Option Register - NOR Flash Mode */ /* Enable Address shift Mode */ #define CSOR_NOR_ADM_SHFT_MODE_EN … /* Page Read Enable from NOR device */ #define CSOR_NOR_PGRD_EN … /* AVD Toggle Enable during Burst Program */ #define CSOR_NOR_AVD_TGL_PGM_EN … /* Address Data Multiplexing Shift */ #define CSOR_NOR_ADM_MASK … #define CSOR_NOR_ADM_SHIFT_SHIFT … #define CSOR_NOR_ADM_SHIFT(n) … /* Type of the NOR device hooked */ #define CSOR_NOR_NOR_MODE_AYSNC_NOR … #define CSOR_NOR_NOR_MODE_AVD_NOR … /* Time for Read Enable High to Output High Impedance */ #define CSOR_NOR_TRHZ_MASK … #define CSOR_NOR_TRHZ_SHIFT … #define CSOR_NOR_TRHZ_20 … #define CSOR_NOR_TRHZ_40 … #define CSOR_NOR_TRHZ_60 … #define CSOR_NOR_TRHZ_80 … #define CSOR_NOR_TRHZ_100 … /* Buffer control disable */ #define CSOR_NOR_BCTLD … /* * Chip Select Option Register - GPCM Mode */ /* GPCM Mode - Normal */ #define CSOR_GPCM_GPMODE_NORMAL … /* GPCM Mode - GenericASIC */ #define CSOR_GPCM_GPMODE_ASIC … /* Parity Mode odd/even */ #define CSOR_GPCM_PARITY_EVEN … /* Parity Checking enable/disable */ #define CSOR_GPCM_PAR_EN … /* GPCM Timeout Count */ #define CSOR_GPCM_GPTO_MASK … #define CSOR_GPCM_GPTO_SHIFT … #define CSOR_GPCM_GPTO(n) … /* GPCM External Access Termination mode for read access */ #define CSOR_GPCM_RGETA_EXT … /* GPCM External Access Termination mode for write access */ #define CSOR_GPCM_WGETA_EXT … /* Address Data Multiplexing Shift */ #define CSOR_GPCM_ADM_MASK … #define CSOR_GPCM_ADM_SHIFT_SHIFT … #define CSOR_GPCM_ADM_SHIFT(n) … /* Generic ASIC Parity error indication delay */ #define CSOR_GPCM_GAPERRD_MASK … #define CSOR_GPCM_GAPERRD_SHIFT … #define CSOR_GPCM_GAPERRD(n) … /* Time for Read Enable High to Output High Impedance */ #define CSOR_GPCM_TRHZ_MASK … #define CSOR_GPCM_TRHZ_20 … #define CSOR_GPCM_TRHZ_40 … #define CSOR_GPCM_TRHZ_60 … #define CSOR_GPCM_TRHZ_80 … #define CSOR_GPCM_TRHZ_100 … /* Buffer control disable */ #define CSOR_GPCM_BCTLD … /* * Ready Busy Status Register (RB_STAT) */ /* CSn is READY */ #define IFC_RB_STAT_READY_CS0 … #define IFC_RB_STAT_READY_CS1 … #define IFC_RB_STAT_READY_CS2 … #define IFC_RB_STAT_READY_CS3 … /* * General Control Register (GCR) */ #define IFC_GCR_MASK … /* reset all IFC hardware */ #define IFC_GCR_SOFT_RST_ALL … /* Turnaroud Time of external buffer */ #define IFC_GCR_TBCTL_TRN_TIME … #define IFC_GCR_TBCTL_TRN_TIME_SHIFT … /* * Common Event and Error Status Register (CM_EVTER_STAT) */ /* Chip select error */ #define IFC_CM_EVTER_STAT_CSER … /* * Common Event and Error Enable Register (CM_EVTER_EN) */ /* Chip select error checking enable */ #define IFC_CM_EVTER_EN_CSEREN … /* * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) */ /* Chip select error interrupt enable */ #define IFC_CM_EVTER_INTR_EN_CSERIREN … /* * Common Transfer Error Attribute Register-0 (CM_ERATTR0) */ /* transaction type of error Read/Write */ #define IFC_CM_ERATTR0_ERTYP_READ … #define IFC_CM_ERATTR0_ERAID … #define IFC_CM_ERATTR0_ERAID_SHIFT … #define IFC_CM_ERATTR0_ESRCID … #define IFC_CM_ERATTR0_ESRCID_SHIFT … /* * Clock Control Register (CCR) */ #define IFC_CCR_MASK … /* Clock division ratio */ #define IFC_CCR_CLK_DIV_MASK … #define IFC_CCR_CLK_DIV_SHIFT … #define IFC_CCR_CLK_DIV(n) … /* IFC Clock Delay */ #define IFC_CCR_CLK_DLY_MASK … #define IFC_CCR_CLK_DLY_SHIFT … #define IFC_CCR_CLK_DLY(n) … /* Invert IFC clock before sending out */ #define IFC_CCR_INV_CLK_EN … /* Fedback IFC Clock */ #define IFC_CCR_FB_IFC_CLK_SEL … /* * Clock Status Register (CSR) */ /* Clk is stable */ #define IFC_CSR_CLK_STAT_STABLE … /* * IFC_NAND Machine Specific Registers */ /* * NAND Configuration Register (NCFGR) */ /* Auto Boot Mode */ #define IFC_NAND_NCFGR_BOOT … /* SRAM Initialization */ #define IFC_NAND_NCFGR_SRAM_INIT_EN … /* Addressing Mode-ROW0+n/COL0 */ #define IFC_NAND_NCFGR_ADDR_MODE_RC0 … /* Addressing Mode-ROW0+n/COL0+n */ #define IFC_NAND_NCFGR_ADDR_MODE_RC1 … /* Number of loop iterations of FIR sequences for multi page operations */ #define IFC_NAND_NCFGR_NUM_LOOP_MASK … #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT … #define IFC_NAND_NCFGR_NUM_LOOP(n) … /* Number of wait cycles */ #define IFC_NAND_NCFGR_NUM_WAIT_MASK … #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT … /* * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) */ /* General purpose FCM flash command bytes CMD0-CMD7 */ #define IFC_NAND_FCR0_CMD0 … #define IFC_NAND_FCR0_CMD0_SHIFT … #define IFC_NAND_FCR0_CMD1 … #define IFC_NAND_FCR0_CMD1_SHIFT … #define IFC_NAND_FCR0_CMD2 … #define IFC_NAND_FCR0_CMD2_SHIFT … #define IFC_NAND_FCR0_CMD3 … #define IFC_NAND_FCR0_CMD3_SHIFT … #define IFC_NAND_FCR1_CMD4 … #define IFC_NAND_FCR1_CMD4_SHIFT … #define IFC_NAND_FCR1_CMD5 … #define IFC_NAND_FCR1_CMD5_SHIFT … #define IFC_NAND_FCR1_CMD6 … #define IFC_NAND_FCR1_CMD6_SHIFT … #define IFC_NAND_FCR1_CMD7 … #define IFC_NAND_FCR1_CMD7_SHIFT … /* * Flash ROW and COL Address Register (ROWn, COLn) */ /* Main/spare region locator */ #define IFC_NAND_COL_MS … /* Column Address */ #define IFC_NAND_COL_CA_MASK … /* * NAND Flash Byte Count Register (NAND_BC) */ /* Byte Count for read/Write */ #define IFC_NAND_BC … /* * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) */ /* NAND Machine specific opcodes OP0-OP14*/ #define IFC_NAND_FIR0_OP0 … #define IFC_NAND_FIR0_OP0_SHIFT … #define IFC_NAND_FIR0_OP1 … #define IFC_NAND_FIR0_OP1_SHIFT … #define IFC_NAND_FIR0_OP2 … #define IFC_NAND_FIR0_OP2_SHIFT … #define IFC_NAND_FIR0_OP3 … #define IFC_NAND_FIR0_OP3_SHIFT … #define IFC_NAND_FIR0_OP4 … #define IFC_NAND_FIR0_OP4_SHIFT … #define IFC_NAND_FIR1_OP5 … #define IFC_NAND_FIR1_OP5_SHIFT … #define IFC_NAND_FIR1_OP6 … #define IFC_NAND_FIR1_OP6_SHIFT … #define IFC_NAND_FIR1_OP7 … #define IFC_NAND_FIR1_OP7_SHIFT … #define IFC_NAND_FIR1_OP8 … #define IFC_NAND_FIR1_OP8_SHIFT … #define IFC_NAND_FIR1_OP9 … #define IFC_NAND_FIR1_OP9_SHIFT … #define IFC_NAND_FIR2_OP10 … #define IFC_NAND_FIR2_OP10_SHIFT … #define IFC_NAND_FIR2_OP11 … #define IFC_NAND_FIR2_OP11_SHIFT … #define IFC_NAND_FIR2_OP12 … #define IFC_NAND_FIR2_OP12_SHIFT … #define IFC_NAND_FIR2_OP13 … #define IFC_NAND_FIR2_OP13_SHIFT … #define IFC_NAND_FIR2_OP14 … #define IFC_NAND_FIR2_OP14_SHIFT … /* * Instruction opcodes to be programmed * in FIR registers- 6bits */ enum ifc_nand_fir_opcodes { … }; /* * NAND Chip Select Register (NAND_CSEL) */ #define IFC_NAND_CSEL … #define IFC_NAND_CSEL_SHIFT … #define IFC_NAND_CSEL_CS0 … #define IFC_NAND_CSEL_CS1 … #define IFC_NAND_CSEL_CS2 … #define IFC_NAND_CSEL_CS3 … /* * NAND Operation Sequence Start (NANDSEQ_STRT) */ /* NAND Flash Operation Start */ #define IFC_NAND_SEQ_STRT_FIR_STRT … /* Automatic Erase */ #define IFC_NAND_SEQ_STRT_AUTO_ERS … /* Automatic Program */ #define IFC_NAND_SEQ_STRT_AUTO_PGM … /* Automatic Copyback */ #define IFC_NAND_SEQ_STRT_AUTO_CPB … /* Automatic Read Operation */ #define IFC_NAND_SEQ_STRT_AUTO_RD … /* Automatic Status Read */ #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD … /* * NAND Event and Error Status Register (NAND_EVTER_STAT) */ /* Operation Complete */ #define IFC_NAND_EVTER_STAT_OPC … /* Flash Timeout Error */ #define IFC_NAND_EVTER_STAT_FTOER … /* Write Protect Error */ #define IFC_NAND_EVTER_STAT_WPER … /* ECC Error */ #define IFC_NAND_EVTER_STAT_ECCER … /* RCW Load Done */ #define IFC_NAND_EVTER_STAT_RCW_DN … /* Boot Loadr Done */ #define IFC_NAND_EVTER_STAT_BOOT_DN … /* Bad Block Indicator search select */ #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE … /* * NAND Flash Page Read Completion Event Status Register * (PGRDCMPL_EVT_STAT) */ #define PGRDCMPL_EVT_STAT_MASK … /* Small Page 0-15 Done */ #define PGRDCMPL_EVT_STAT_SECTION_SP(n) … /* Large Page(2K) 0-3 Done */ #define PGRDCMPL_EVT_STAT_LP_2K(n) … /* Large Page(4K) 0-1 Done */ #define PGRDCMPL_EVT_STAT_LP_4K(n) … /* * NAND Event and Error Enable Register (NAND_EVTER_EN) */ /* Operation complete event enable */ #define IFC_NAND_EVTER_EN_OPC_EN … /* Page read complete event enable */ #define IFC_NAND_EVTER_EN_PGRDCMPL_EN … /* Flash Timeout error enable */ #define IFC_NAND_EVTER_EN_FTOER_EN … /* Write Protect error enable */ #define IFC_NAND_EVTER_EN_WPER_EN … /* ECC error logging enable */ #define IFC_NAND_EVTER_EN_ECCER_EN … /* * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) */ /* Enable interrupt for operation complete */ #define IFC_NAND_EVTER_INTR_OPCIR_EN … /* Enable interrupt for Page read complete */ #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN … /* Enable interrupt for Flash timeout error */ #define IFC_NAND_EVTER_INTR_FTOERIR_EN … /* Enable interrupt for Write protect error */ #define IFC_NAND_EVTER_INTR_WPERIR_EN … /* Enable interrupt for ECC error*/ #define IFC_NAND_EVTER_INTR_ECCERIR_EN … /* * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) */ #define IFC_NAND_ERATTR0_MASK … /* Error on CS0-3 for NAND */ #define IFC_NAND_ERATTR0_ERCS_CS0 … #define IFC_NAND_ERATTR0_ERCS_CS1 … #define IFC_NAND_ERATTR0_ERCS_CS2 … #define IFC_NAND_ERATTR0_ERCS_CS3 … /* Transaction type of error Read/Write */ #define IFC_NAND_ERATTR0_ERTTYPE_READ … /* * NAND Flash Status Register (NAND_FSR) */ /* First byte of data read from read status op */ #define IFC_NAND_NFSR_RS0 … /* Second byte of data read from read status op */ #define IFC_NAND_NFSR_RS1 … /* * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) */ /* Number of ECC errors on sector n (n = 0-15) */ #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK … #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT … #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK … #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT … #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK … #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT … #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK … #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT … #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK … #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT … #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK … #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT … #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK … #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT … #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK … #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT … #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK … #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT … #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK … #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT … #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK … #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT … #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK … #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT … #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK … #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT … #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK … #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT … #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK … #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT … #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK … #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT … /* * NAND Control Register (NANDCR) */ #define IFC_NAND_NCR_FTOCNT_MASK … #define IFC_NAND_NCR_FTOCNT_SHIFT … #define IFC_NAND_NCR_FTOCNT(n) … /* * NAND_AUTOBOOT_TRGR */ /* Trigger RCW load */ #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD … /* Trigget Auto Boot */ #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD … /* * NAND_MDR */ /* 1st read data byte when opcode SBRD */ #define IFC_NAND_MDR_RDATA0 … /* 2nd read data byte when opcode SBRD */ #define IFC_NAND_MDR_RDATA1 … /* * NOR Machine Specific Registers */ /* * NOR Event and Error Status Register (NOR_EVTER_STAT) */ /* NOR Command Sequence Operation Complete */ #define IFC_NOR_EVTER_STAT_OPC_NOR … /* Write Protect Error */ #define IFC_NOR_EVTER_STAT_WPER … /* Command Sequence Timeout Error */ #define IFC_NOR_EVTER_STAT_STOER … /* * NOR Event and Error Enable Register (NOR_EVTER_EN) */ /* NOR Command Seq complete event enable */ #define IFC_NOR_EVTER_EN_OPCEN_NOR … /* Write Protect Error Checking Enable */ #define IFC_NOR_EVTER_EN_WPEREN … /* Timeout Error Enable */ #define IFC_NOR_EVTER_EN_STOEREN … /* * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) */ /* Enable interrupt for OPC complete */ #define IFC_NOR_EVTER_INTR_OPCEN_NOR … /* Enable interrupt for write protect error */ #define IFC_NOR_EVTER_INTR_WPEREN … /* Enable interrupt for timeout error */ #define IFC_NOR_EVTER_INTR_STOEREN … /* * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) */ /* Source ID for error transaction */ #define IFC_NOR_ERATTR0_ERSRCID … /* AXI ID for error transation */ #define IFC_NOR_ERATTR0_ERAID … /* Chip select corresponds to NOR error */ #define IFC_NOR_ERATTR0_ERCS_CS0 … #define IFC_NOR_ERATTR0_ERCS_CS1 … #define IFC_NOR_ERATTR0_ERCS_CS2 … #define IFC_NOR_ERATTR0_ERCS_CS3 … /* Type of transaction read/write */ #define IFC_NOR_ERATTR0_ERTYPE_READ … /* * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) */ #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP … #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER … /* * NOR Control Register (NORCR) */ #define IFC_NORCR_MASK … /* No. of Address/Data Phase */ #define IFC_NORCR_NUM_PHASE_MASK … #define IFC_NORCR_NUM_PHASE_SHIFT … #define IFC_NORCR_NUM_PHASE(n) … /* Sequence Timeout Count */ #define IFC_NORCR_STOCNT_MASK … #define IFC_NORCR_STOCNT_SHIFT … #define IFC_NORCR_STOCNT(n) … /* * GPCM Machine specific registers */ /* * GPCM Event and Error Status Register (GPCM_EVTER_STAT) */ /* Timeout error */ #define IFC_GPCM_EVTER_STAT_TOER … /* Parity error */ #define IFC_GPCM_EVTER_STAT_PER … /* * GPCM Event and Error Enable Register (GPCM_EVTER_EN) */ /* Timeout error enable */ #define IFC_GPCM_EVTER_EN_TOER_EN … /* Parity error enable */ #define IFC_GPCM_EVTER_EN_PER_EN … /* * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) */ /* Enable Interrupt for timeout error */ #define IFC_GPCM_EEIER_TOERIR_EN … /* Enable Interrupt for Parity error */ #define IFC_GPCM_EEIER_PERIR_EN … /* * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) */ /* Source ID for error transaction */ #define IFC_GPCM_ERATTR0_ERSRCID … /* AXI ID for error transaction */ #define IFC_GPCM_ERATTR0_ERAID … /* Chip select corresponds to GPCM error */ #define IFC_GPCM_ERATTR0_ERCS_CS0 … #define IFC_GPCM_ERATTR0_ERCS_CS1 … #define IFC_GPCM_ERATTR0_ERCS_CS2 … #define IFC_GPCM_ERATTR0_ERCS_CS3 … /* Type of transaction read/Write */ #define IFC_GPCM_ERATTR0_ERTYPE_READ … /* * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) */ /* On which beat of address/data parity error is observed */ #define IFC_GPCM_ERATTR2_PERR_BEAT … /* Parity Error on byte */ #define IFC_GPCM_ERATTR2_PERR_BYTE … /* Parity Error reported in addr or data phase */ #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE … /* * GPCM Status Register (GPCM_STAT) */ #define IFC_GPCM_STAT_BSY … /* * IFC Controller NAND Machine registers */ struct fsl_ifc_nand { … }; /* * IFC controller NOR Machine registers */ struct fsl_ifc_nor { … }; /* * IFC controller GPCM Machine registers */ struct fsl_ifc_gpcm { … }; /* * IFC Controller Registers */ struct fsl_ifc_global { … }; struct fsl_ifc_runtime { … }; extern unsigned int convert_ifc_address(phys_addr_t addr_base); extern int fsl_ifc_find(phys_addr_t addr_base); /* overview of the fsl ifc controller */ struct fsl_ifc_ctrl { … }; extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev; static inline u32 ifc_in32(void __iomem *addr) { … } static inline u16 ifc_in16(void __iomem *addr) { … } static inline u8 ifc_in8(void __iomem *addr) { … } static inline void ifc_out32(u32 val, void __iomem *addr) { … } static inline void ifc_out16(u16 val, void __iomem *addr) { … } static inline void ifc_out8(u8 val, void __iomem *addr) { … } #endif /* __ASM_FSL_IFC_H */
Codebase Browser
linux