// SPDX-License-Identifier: GPL-2.0-or-later /* * NXP LPC32XX NAND SLC driver * * Authors: * Kevin Wells <[email protected]> * Roland Stigge <[email protected]> * * Copyright © 2011 NXP Semiconductors * Copyright © 2012 Roland Stigge */ #include <linux/slab.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/mtd/mtd.h> #include <linux/mtd/rawnand.h> #include <linux/mtd/partitions.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/mm.h> #include <linux/dma-mapping.h> #include <linux/dmaengine.h> #include <linux/gpio/consumer.h> #include <linux/of.h> #include <linux/mtd/lpc32xx_slc.h> #define LPC32XX_MODNAME … /********************************************************************** * SLC NAND controller register offsets **********************************************************************/ #define SLC_DATA(x) … #define SLC_ADDR(x) … #define SLC_CMD(x) … #define SLC_STOP(x) … #define SLC_CTRL(x) … #define SLC_CFG(x) … #define SLC_STAT(x) … #define SLC_INT_STAT(x) … #define SLC_IEN(x) … #define SLC_ISR(x) … #define SLC_ICR(x) … #define SLC_TAC(x) … #define SLC_TC(x) … #define SLC_ECC(x) … #define SLC_DMA_DATA(x) … /********************************************************************** * slc_ctrl register definitions **********************************************************************/ #define SLCCTRL_SW_RESET … #define SLCCTRL_ECC_CLEAR … #define SLCCTRL_DMA_START … /********************************************************************** * slc_cfg register definitions **********************************************************************/ #define SLCCFG_CE_LOW … #define SLCCFG_DMA_ECC … #define SLCCFG_ECC_EN … #define SLCCFG_DMA_BURST … #define SLCCFG_DMA_DIR … #define SLCCFG_WIDTH … /********************************************************************** * slc_stat register definitions **********************************************************************/ #define SLCSTAT_DMA_FIFO … #define SLCSTAT_SLC_FIFO … #define SLCSTAT_NAND_READY … /********************************************************************** * slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions **********************************************************************/ #define SLCSTAT_INT_TC … #define SLCSTAT_INT_RDY_EN … /********************************************************************** * slc_tac register definitions **********************************************************************/ /* Computation of clock cycles on basis of controller and device clock rates */ #define SLCTAC_CLOCKS(c, n, s) … /* Clock setting for RDY write sample wait time in 2*n clocks */ #define SLCTAC_WDR(n) … /* Write pulse width in clock cycles, 1 to 16 clocks */ #define SLCTAC_WWIDTH(c, n) … /* Write hold time of control and data signals, 1 to 16 clocks */ #define SLCTAC_WHOLD(c, n) … /* Write setup time of control and data signals, 1 to 16 clocks */ #define SLCTAC_WSETUP(c, n) … /* Clock setting for RDY read sample wait time in 2*n clocks */ #define SLCTAC_RDR(n) … /* Read pulse width in clock cycles, 1 to 16 clocks */ #define SLCTAC_RWIDTH(c, n) … /* Read hold time of control and data signals, 1 to 16 clocks */ #define SLCTAC_RHOLD(c, n) … /* Read setup time of control and data signals, 1 to 16 clocks */ #define SLCTAC_RSETUP(c, n) … /********************************************************************** * slc_ecc register definitions **********************************************************************/ /* ECC line party fetch macro */ #define SLCECC_TO_LINEPAR(n) … #define SLCECC_TO_COLPAR(n) … /* * DMA requires storage space for the DMA local buffer and the hardware ECC * storage area. The DMA local buffer is only used if DMA mapping fails * during runtime. */ #define LPC32XX_DMA_DATA_SIZE … #define LPC32XX_ECC_SAVE_SIZE … /* Number of bytes used for ECC stored in NAND per 256 bytes */ #define LPC32XX_SLC_DEV_ECC_BYTES … /* * If the NAND base clock frequency can't be fetched, this frequency will be * used instead as the base. This rate is used to setup the timing registers * used for NAND accesses. */ #define LPC32XX_DEF_BUS_RATE … /* Milliseconds for DMA FIFO timeout (unlikely anyway) */ #define LPC32XX_DMA_TIMEOUT … /* * NAND ECC Layout for small page NAND devices * Note: For large and huge page devices, the default layouts are used */ static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *oobregion) { … } static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section, struct mtd_oob_region *oobregion) { … } static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = …; static u8 bbt_pattern[] = …; static u8 mirror_pattern[] = …; /* * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6 * Note: Large page devices used the default layout */ static struct nand_bbt_descr bbt_smallpage_main_descr = …; static struct nand_bbt_descr bbt_smallpage_mirror_descr = …; /* * NAND platform configuration structure */ struct lpc32xx_nand_cfg_slc { … }; struct lpc32xx_nand_host { … }; static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host) { … } /* * Hardware specific access to control lines */ static void lpc32xx_nand_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl) { … } /* * Read the Device Ready pin */ static int lpc32xx_nand_device_ready(struct nand_chip *chip) { … } /* * Enable NAND write protect */ static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host) { … } /* * Disable NAND write protect */ static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host) { … } /* * Prepares SLC for transfers with H/W ECC enabled */ static void lpc32xx_nand_ecc_enable(struct nand_chip *chip, int mode) { … } /* * Calculates the ECC for the data */ static int lpc32xx_nand_ecc_calculate(struct nand_chip *chip, const unsigned char *buf, unsigned char *code) { … } /* * Read a single byte from NAND device */ static uint8_t lpc32xx_nand_read_byte(struct nand_chip *chip) { … } /* * Simple device read without ECC */ static void lpc32xx_nand_read_buf(struct nand_chip *chip, u_char *buf, int len) { … } /* * Simple device write without ECC */ static void lpc32xx_nand_write_buf(struct nand_chip *chip, const uint8_t *buf, int len) { … } /* * Read the OOB data from the device without ECC using FIFO method */ static int lpc32xx_nand_read_oob_syndrome(struct nand_chip *chip, int page) { … } /* * Write the OOB data to the device without ECC using FIFO method */ static int lpc32xx_nand_write_oob_syndrome(struct nand_chip *chip, int page) { … } /* * Fills in the ECC fields in the OOB buffer with the hardware generated ECC */ static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count) { … } static void lpc32xx_dma_complete_func(void *completion) { … } static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma, void *mem, int len, enum dma_transfer_direction dir) { … } /* * DMA read/write transfers with ECC support */ static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages, int read) { … } /* * Read the data and OOB data from the device, use ECC correction with the * data, disable ECC for the OOB data */ static int lpc32xx_nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { … } /* * Read the data and OOB data from the device, no ECC correction with the * data or OOB data */ static int lpc32xx_nand_read_page_raw_syndrome(struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { … } /* * Write the data and OOB data to the device, use ECC with the data, * disable ECC for the OOB data */ static int lpc32xx_nand_write_page_syndrome(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page) { … } /* * Write the data and OOB data to the device, no ECC correction with the * data or OOB data */ static int lpc32xx_nand_write_page_raw_syndrome(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page) { … } static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host) { … } static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev) { … } static int lpc32xx_nand_attach_chip(struct nand_chip *chip) { … } static const struct nand_controller_ops lpc32xx_nand_controller_ops = …; /* * Probe for NAND controller */ static int lpc32xx_nand_probe(struct platform_device *pdev) { … } /* * Remove NAND device. */ static void lpc32xx_nand_remove(struct platform_device *pdev) { … } static int lpc32xx_nand_resume(struct platform_device *pdev) { … } static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm) { … } static const struct of_device_id lpc32xx_nand_match[] = …; MODULE_DEVICE_TABLE(of, lpc32xx_nand_match); static struct platform_driver lpc32xx_nand_driver = …; module_platform_driver(…) …; MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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