/* SPDX-License-Identifier: GPL-2.0 * * SuperH FLCTL nand controller * * Copyright © 2008 Renesas Solutions Corp. */ #ifndef __SH_FLCTL_H__ #define __SH_FLCTL_H__ #include <linux/completion.h> #include <linux/mtd/mtd.h> #include <linux/mtd/rawnand.h> #include <linux/mtd/partitions.h> #include <linux/pm_qos.h> /* FLCTL registers */ #define FLCMNCR(f) … #define FLCMDCR(f) … #define FLCMCDR(f) … #define FLADR(f) … #define FLADR2(f) … #define FLDATAR(f) … #define FLDTCNTR(f) … #define FLINTDMACR(f) … #define FLBSYTMR(f) … #define FLBSYCNT(f) … #define FLDTFIFO(f) … #define FLECFIFO(f) … #define FLTRCR(f) … #define FLHOLDCR(f) … #define FL4ECCRESULT0(f) … #define FL4ECCRESULT1(f) … #define FL4ECCRESULT2(f) … #define FL4ECCRESULT3(f) … #define FL4ECCCR(f) … #define FL4ECCCNT(f) … #define FLERRADR(f) … /* FLCMNCR control bits */ #define _4ECCCNTEN … #define _4ECCEN … #define _4ECCCORRECT … #define SHBUSSEL … #define SEL_16BIT … #define SNAND_E … #define QTSEL_E … #define ENDIAN … #define FCKSEL_E … #define ACM_SACCES_MODE … #define NANWF_E … #define SE_D … #define CE1_ENABLE … #define CE0_ENABLE … #define TYPESEL_SET … /* * Clock settings using the PULSEx registers from FLCMNCR * * Some hardware uses bits called PULSEx instead of FCKSEL_E and QTSEL_E * to control the clock divider used between the High-Speed Peripheral Clock * and the FLCTL internal clock. If so, use CLK_8_BIT_xxx for connecting 8 bit * and CLK_16_BIT_xxx for connecting 16 bit bus bandwith NAND chips. For the 16 * bit version the divider is seperate for the pulse width of high and low * signals. */ #define PULSE3 … #define PULSE2 … #define PULSE1 … #define PULSE0 … #define CLK_8B_0_5 … #define CLK_8B_1 … #define CLK_8B_1_5 … #define CLK_8B_2 … #define CLK_8B_3 … #define CLK_8B_4 … #define CLK_16B_6L_2H … #define CLK_16B_9L_3H … #define CLK_16B_12L_4H … /* FLCMDCR control bits */ #define ADRCNT2_E … #define ADRMD_E … #define CDSRC_E … #define DOSR_E … #define SELRW … #define DOADR_E … #define ADRCNT_1 … #define ADRCNT_2 … #define ADRCNT_3 … #define ADRCNT_4 … #define DOCMD2_E … #define DOCMD1_E … /* FLINTDMACR control bits */ #define ESTERINTE … #define AC1CLR … #define AC0CLR … #define DREQ0EN … #define ECERB … #define STERB … #define STERINTE … /* FLTRCR control bits */ #define TRSTRT … #define TREND … /* * FLHOLDCR control bits * * HOLDEN: Bus Occupancy Enable (inverted) * Enable this bit when the external bus might be used in between transfers. * If not set and the bus gets used by other modules, a deadlock occurs. */ #define HOLDEN … /* FL4ECCCR control bits */ #define _4ECCFA … #define _4ECCEND … #define _4ECCEXST … #define LOOP_TIMEOUT_MAX … enum flctl_ecc_res_t { … }; struct dma_chan; struct sh_flctl { … }; struct sh_flctl_platform_data { … }; static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo) { … } #endif /* __SH_FLCTL_H__ */
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