// SPDX-License-Identifier: GPL-2.0-or-later /* * Hisilicon NAND Flash controller driver * * Copyright © 2012-2014 HiSilicon Technologies Co., Ltd. * http://www.hisilicon.com * * Author: Zhou Wang <[email protected]> * The initial developer of the original code is Zhiyong Cai * <[email protected]> */ #include <linux/of.h> #include <linux/mtd/mtd.h> #include <linux/sizes.h> #include <linux/clk.h> #include <linux/slab.h> #include <linux/module.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/mtd/rawnand.h> #include <linux/dma-mapping.h> #include <linux/platform_device.h> #include <linux/mtd/partitions.h> #define HINFC504_MAX_CHIP … #define HINFC504_W_LATCH … #define HINFC504_R_LATCH … #define HINFC504_RW_LATCH … #define HINFC504_NFC_TIMEOUT … #define HINFC504_NFC_PM_TIMEOUT … #define HINFC504_NFC_DMA_TIMEOUT … #define HINFC504_CHIP_DELAY … #define HINFC504_REG_BASE_ADDRESS_LEN … #define HINFC504_BUFFER_BASE_ADDRESS_LEN … #define HINFC504_ADDR_CYCLE_MASK … #define HINFC504_CON … #define HINFC504_CON_OP_MODE_NORMAL … #define HINFC504_CON_PAGEISZE_SHIFT … #define HINFC504_CON_PAGESIZE_MASK … #define HINFC504_CON_BUS_WIDTH … #define HINFC504_CON_READY_BUSY_SEL … #define HINFC504_CON_ECCTYPE_SHIFT … #define HINFC504_CON_ECCTYPE_MASK … #define HINFC504_PWIDTH … #define SET_HINFC504_PWIDTH(_w_lcnt, _r_lcnt, _rw_hcnt) … #define HINFC504_CMD … #define HINFC504_ADDRL … #define HINFC504_ADDRH … #define HINFC504_DATA_NUM … #define HINFC504_OP … #define HINFC504_OP_READ_DATA_EN … #define HINFC504_OP_WAIT_READY_EN … #define HINFC504_OP_CMD2_EN … #define HINFC504_OP_WRITE_DATA_EN … #define HINFC504_OP_ADDR_EN … #define HINFC504_OP_CMD1_EN … #define HINFC504_OP_NF_CS_SHIFT … #define HINFC504_OP_NF_CS_MASK … #define HINFC504_OP_ADDR_CYCLE_SHIFT … #define HINFC504_OP_ADDR_CYCLE_MASK … #define HINFC504_STATUS … #define HINFC504_READY … #define HINFC504_INTEN … #define HINFC504_INTEN_DMA … #define HINFC504_INTEN_UE … #define HINFC504_INTEN_CE … #define HINFC504_INTS … #define HINFC504_INTS_DMA … #define HINFC504_INTS_UE … #define HINFC504_INTS_CE … #define HINFC504_INTCLR … #define HINFC504_INTCLR_DMA … #define HINFC504_INTCLR_UE … #define HINFC504_INTCLR_CE … #define HINFC504_ECC_STATUS … #define HINFC504_ECC_16_BIT_SHIFT … #define HINFC504_DMA_CTRL … #define HINFC504_DMA_CTRL_DMA_START … #define HINFC504_DMA_CTRL_WE … #define HINFC504_DMA_CTRL_DATA_AREA_EN … #define HINFC504_DMA_CTRL_OOB_AREA_EN … #define HINFC504_DMA_CTRL_BURST4_EN … #define HINFC504_DMA_CTRL_BURST8_EN … #define HINFC504_DMA_CTRL_BURST16_EN … #define HINFC504_DMA_CTRL_ADDR_NUM_SHIFT … #define HINFC504_DMA_CTRL_ADDR_NUM_MASK … #define HINFC504_DMA_CTRL_CS_SHIFT … #define HINFC504_DMA_CTRL_CS_MASK … #define HINFC504_DMA_ADDR_DATA … #define HINFC504_DMA_ADDR_OOB … #define HINFC504_DMA_LEN … #define HINFC504_DMA_LEN_OOB_SHIFT … #define HINFC504_DMA_LEN_OOB_MASK … #define HINFC504_DMA_PARA … #define HINFC504_DMA_PARA_DATA_RW_EN … #define HINFC504_DMA_PARA_OOB_RW_EN … #define HINFC504_DMA_PARA_DATA_EDC_EN … #define HINFC504_DMA_PARA_OOB_EDC_EN … #define HINFC504_DMA_PARA_DATA_ECC_EN … #define HINFC504_DMA_PARA_OOB_ECC_EN … #define HINFC_VERSION … #define HINFC504_LOG_READ_ADDR … #define HINFC504_LOG_READ_LEN … #define HINFC504_NANDINFO_LEN … struct hinfc_host { … }; static inline unsigned int hinfc_read(struct hinfc_host *host, unsigned int reg) { … } static inline void hinfc_write(struct hinfc_host *host, unsigned int value, unsigned int reg) { … } static void wait_controller_finished(struct hinfc_host *host) { … } static void hisi_nfc_dma_transfer(struct hinfc_host *host, int todev) { … } static int hisi_nfc_send_cmd_pageprog(struct hinfc_host *host) { … } static int hisi_nfc_send_cmd_readstart(struct hinfc_host *host) { … } static int hisi_nfc_send_cmd_erase(struct hinfc_host *host) { … } static int hisi_nfc_send_cmd_readid(struct hinfc_host *host) { … } static int hisi_nfc_send_cmd_status(struct hinfc_host *host) { … } static int hisi_nfc_send_cmd_reset(struct hinfc_host *host, int chipselect) { … } static void hisi_nfc_select_chip(struct nand_chip *chip, int chipselect) { … } static uint8_t hisi_nfc_read_byte(struct nand_chip *chip) { … } static void hisi_nfc_write_buf(struct nand_chip *chip, const uint8_t *buf, int len) { … } static void hisi_nfc_read_buf(struct nand_chip *chip, uint8_t *buf, int len) { … } static void set_addr(struct mtd_info *mtd, int column, int page_addr) { … } static void hisi_nfc_cmdfunc(struct nand_chip *chip, unsigned command, int column, int page_addr) { … } static irqreturn_t hinfc_irq_handle(int irq, void *devid) { … } static int hisi_nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { … } static int hisi_nand_read_oob(struct nand_chip *chip, int page) { … } static int hisi_nand_write_page_hwecc(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page) { … } static void hisi_nfc_host_init(struct hinfc_host *host) { … } static int hisi_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *oobregion) { … } static int hisi_ooblayout_free(struct mtd_info *mtd, int section, struct mtd_oob_region *oobregion) { … } static const struct mtd_ooblayout_ops hisi_ooblayout_ops = …; static int hisi_nfc_ecc_probe(struct hinfc_host *host) { … } static int hisi_nfc_attach_chip(struct nand_chip *chip) { … } static const struct nand_controller_ops hisi_nfc_controller_ops = …; static int hisi_nfc_probe(struct platform_device *pdev) { … } static void hisi_nfc_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int hisi_nfc_suspend(struct device *dev) { … } static int hisi_nfc_resume(struct device *dev) { … } #endif static SIMPLE_DEV_PM_OPS(hisi_nfc_pm_ops, hisi_nfc_suspend, hisi_nfc_resume); static const struct of_device_id nfc_id_table[] = …; MODULE_DEVICE_TABLE(of, nfc_id_table); static struct platform_driver hisi_nfc_driver = …; module_platform_driver(…) …; MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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