// SPDX-License-Identifier: GPL-2.0 /* * Evatronix/Renesas R-Car Gen3, RZ/N1D, RZ/N1S, RZ/N1L NAND controller driver * * Copyright (C) 2021 Schneider Electric * Author: Miquel RAYNAL <[email protected]> */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/dma-mapping.h> #include <linux/interrupt.h> #include <linux/iopoll.h> #include <linux/module.h> #include <linux/mtd/mtd.h> #include <linux/mtd/rawnand.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/slab.h> #define COMMAND_REG … #define COMMAND_SEQ(x) … #define COMMAND_SEQ_10 … #define COMMAND_SEQ_12 … #define COMMAND_SEQ_18 … #define COMMAND_SEQ_19 … #define COMMAND_SEQ_GEN_IN … #define COMMAND_SEQ_GEN_OUT … #define COMMAND_SEQ_READ_PAGE … #define COMMAND_SEQ_WRITE_PAGE … #define COMMAND_INPUT_SEL_AHBS … #define COMMAND_INPUT_SEL_DMA … #define COMMAND_FIFO_SEL … #define COMMAND_DATA_SEL … #define COMMAND_0(x) … #define COMMAND_1(x) … #define COMMAND_2(x) … #define CONTROL_REG … #define CONTROL_CHECK_RB_LINE … #define CONTROL_ECC_BLOCK_SIZE(x) … #define CONTROL_ECC_BLOCK_SIZE_256 … #define CONTROL_ECC_BLOCK_SIZE_512 … #define CONTROL_ECC_BLOCK_SIZE_1024 … #define CONTROL_INT_EN … #define CONTROL_ECC_EN … #define CONTROL_BLOCK_SIZE(x) … #define CONTROL_BLOCK_SIZE_32P … #define CONTROL_BLOCK_SIZE_64P … #define CONTROL_BLOCK_SIZE_128P … #define CONTROL_BLOCK_SIZE_256P … #define STATUS_REG … #define MEM_RDY(cs, reg) … #define CTRL_RDY(reg) … #define ECC_CTRL_REG … #define ECC_CTRL_CAP(x) … #define ECC_CTRL_CAP_2B … #define ECC_CTRL_CAP_4B … #define ECC_CTRL_CAP_8B … #define ECC_CTRL_CAP_16B … #define ECC_CTRL_CAP_24B … #define ECC_CTRL_CAP_32B … #define ECC_CTRL_ERR_THRESHOLD(x) … #define INT_MASK_REG … #define INT_STATUS_REG … #define INT_CMD_END … #define INT_DMA_END … #define INT_MEM_RDY(cs) … #define INT_DMA_ENDED … #define MEM_IS_RDY(cs, reg) … #define DMA_HAS_ENDED(reg) … #define ECC_OFFSET_REG … #define ECC_OFFSET(x) … #define ECC_STAT_REG … #define ECC_STAT_CORRECTABLE(cs, reg) … #define ECC_STAT_UNCORRECTABLE(cs, reg) … #define ADDR0_COL_REG … #define ADDR0_COL(x) … #define ADDR0_ROW_REG … #define ADDR0_ROW(x) … #define ADDR1_COL_REG … #define ADDR1_COL(x) … #define ADDR1_ROW_REG … #define ADDR1_ROW(x) … #define FIFO_DATA_REG … #define DATA_REG … #define DATA_REG_SIZE_REG … #define DMA_ADDR_LOW_REG … #define DMA_ADDR_HIGH_REG … #define DMA_CNT_REG … #define DMA_CTRL_REG … #define DMA_CTRL_INCREMENT_BURST_4 … #define DMA_CTRL_REGISTER_MANAGED_MODE … #define DMA_CTRL_START … #define MEM_CTRL_REG … #define MEM_CTRL_CS(cs) … #define MEM_CTRL_DIS_WP(cs) … #define DATA_SIZE_REG … #define DATA_SIZE(x) … #define TIMINGS_ASYN_REG … #define TIMINGS_ASYN_TRWP(x) … #define TIMINGS_ASYN_TRWH(x) … #define TIM_SEQ0_REG … #define TIM_SEQ0_TCCS(x) … #define TIM_SEQ0_TADL(x) … #define TIM_SEQ0_TRHW(x) … #define TIM_SEQ0_TWHR(x) … #define TIM_SEQ1_REG … #define TIM_SEQ1_TWB(x) … #define TIM_SEQ1_TRR(x) … #define TIM_SEQ1_TWW(x) … #define TIM_GEN_SEQ0_REG … #define TIM_GEN_SEQ0_D0(x) … #define TIM_GEN_SEQ0_D1(x) … #define TIM_GEN_SEQ0_D2(x) … #define TIM_GEN_SEQ0_D3(x) … #define TIM_GEN_SEQ1_REG … #define TIM_GEN_SEQ1_D4(x) … #define TIM_GEN_SEQ1_D5(x) … #define TIM_GEN_SEQ1_D6(x) … #define TIM_GEN_SEQ1_D7(x) … #define TIM_GEN_SEQ2_REG … #define TIM_GEN_SEQ2_D8(x) … #define TIM_GEN_SEQ2_D9(x) … #define TIM_GEN_SEQ2_D10(x) … #define TIM_GEN_SEQ2_D11(x) … #define FIFO_INIT_REG … #define FIFO_INIT … #define FIFO_STATE_REG … #define FIFO_STATE_R_EMPTY(reg) … #define FIFO_STATE_W_FULL(reg) … #define FIFO_STATE_C_EMPTY(reg) … #define FIFO_STATE_R_FULL(reg) … #define FIFO_STATE_W_EMPTY(reg) … #define GEN_SEQ_CTRL_REG … #define GEN_SEQ_CMD0_EN … #define GEN_SEQ_CMD1_EN … #define GEN_SEQ_CMD2_EN … #define GEN_SEQ_CMD3_EN … #define GEN_SEQ_COL_A0(x) … #define GEN_SEQ_COL_A1(x) … #define GEN_SEQ_ROW_A0(x) … #define GEN_SEQ_ROW_A1(x) … #define GEN_SEQ_DATA_EN … #define GEN_SEQ_DELAY_EN(x) … #define GEN_SEQ_DELAY0_EN … #define GEN_SEQ_DELAY1_EN … #define GEN_SEQ_IMD_SEQ … #define GEN_SEQ_COMMAND_3(x) … #define DMA_TLVL_REG … #define DMA_TLVL(x) … #define DMA_TLVL_MAX … #define TIM_GEN_SEQ3_REG … #define TIM_GEN_SEQ3_D12(x) … #define ECC_CNT_REG … #define ECC_CNT(cs, reg) … #define RNANDC_CS_NUM … #define TO_CYCLES64(ps, period_ns) … struct rnand_chip_sel { … }; struct rnand_chip { … }; struct rnandc { … }; struct rnandc_op { … }; static inline struct rnandc *to_rnandc(struct nand_controller *ctrl) { … } static inline struct rnand_chip *to_rnand(struct nand_chip *chip) { … } static inline unsigned int to_rnandc_cs(struct rnand_chip *nand) { … } static void rnandc_dis_correction(struct rnandc *rnandc) { … } static void rnandc_en_correction(struct rnandc *rnandc) { … } static void rnandc_clear_status(struct rnandc *rnandc) { … } static void rnandc_dis_interrupts(struct rnandc *rnandc) { … } static void rnandc_en_interrupts(struct rnandc *rnandc, u32 val) { … } static void rnandc_clear_fifo(struct rnandc *rnandc) { … } static void rnandc_select_target(struct nand_chip *chip, int die_nr) { … } static void rnandc_trigger_op(struct rnandc *rnandc, struct rnandc_op *rop) { … } static void rnandc_trigger_dma(struct rnandc *rnandc) { … } static irqreturn_t rnandc_irq_handler(int irq, void *private) { … } static int rnandc_wait_end_of_op(struct rnandc *rnandc, struct nand_chip *chip) { … } static int rnandc_wait_end_of_io(struct rnandc *rnandc, struct nand_chip *chip) { … } static int rnandc_read_page_hw_ecc(struct nand_chip *chip, u8 *buf, int oob_required, int page) { … } static int rnandc_read_subpage_hw_ecc(struct nand_chip *chip, u32 req_offset, u32 req_len, u8 *bufpoi, int page) { … } static int rnandc_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf, int oob_required, int page) { … } static int rnandc_write_subpage_hw_ecc(struct nand_chip *chip, u32 req_offset, u32 req_len, const u8 *bufpoi, int oob_required, int page) { … } /* * This controller is simple enough and thus does not need to use the parser * provided by the core, instead, handle every situation here. */ static int rnandc_exec_op(struct nand_chip *chip, const struct nand_operation *op, bool check_only) { … } static int rnandc_setup_interface(struct nand_chip *chip, int chipnr, const struct nand_interface_config *conf) { … } static int rnandc_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *oobregion) { … } static int rnandc_ooblayout_free(struct mtd_info *mtd, int section, struct mtd_oob_region *oobregion) { … } static const struct mtd_ooblayout_ops rnandc_ooblayout_ops = …; static int rnandc_hw_ecc_controller_init(struct nand_chip *chip) { … } static int rnandc_ecc_init(struct nand_chip *chip) { … } static int rnandc_attach_chip(struct nand_chip *chip) { … } static const struct nand_controller_ops rnandc_ops = …; static int rnandc_alloc_dma_buf(struct rnandc *rnandc, struct mtd_info *new_mtd) { … } static int rnandc_chip_init(struct rnandc *rnandc, struct device_node *np) { … } static void rnandc_chips_cleanup(struct rnandc *rnandc) { … } static int rnandc_chips_init(struct rnandc *rnandc) { … } static int rnandc_probe(struct platform_device *pdev) { … } static void rnandc_remove(struct platform_device *pdev) { … } static const struct of_device_id rnandc_id_table[] = …; MODULE_DEVICE_TABLE(of, rnandc_id_table); static struct platform_driver rnandc_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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