/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2014 Freescale Semiconductor, Inc. */ #ifndef __LINUX_MTD_SPI_NOR_H #define __LINUX_MTD_SPI_NOR_H #include <linux/bitops.h> #include <linux/mtd/mtd.h> #include <linux/spi/spi-mem.h> /* * Note on opcode nomenclature: some opcodes have a format like * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number * of I/O lines used for the opcode, address, and data (respectively). The * FUNCTION has an optional suffix of '4', to represent an opcode which * requires a 4-byte (32-bit) address. */ /* Flash opcodes. */ #define SPINOR_OP_WRDI … #define SPINOR_OP_WREN … #define SPINOR_OP_RDSR … #define SPINOR_OP_WRSR … #define SPINOR_OP_RDSR2 … #define SPINOR_OP_WRSR2 … #define SPINOR_OP_READ … #define SPINOR_OP_READ_FAST … #define SPINOR_OP_READ_1_1_2 … #define SPINOR_OP_READ_1_2_2 … #define SPINOR_OP_READ_1_1_4 … #define SPINOR_OP_READ_1_4_4 … #define SPINOR_OP_READ_1_1_8 … #define SPINOR_OP_READ_1_8_8 … #define SPINOR_OP_PP … #define SPINOR_OP_PP_1_1_4 … #define SPINOR_OP_PP_1_4_4 … #define SPINOR_OP_PP_1_1_8 … #define SPINOR_OP_PP_1_8_8 … #define SPINOR_OP_BE_4K … #define SPINOR_OP_BE_4K_PMC … #define SPINOR_OP_BE_32K … #define SPINOR_OP_CHIP_ERASE … #define SPINOR_OP_SE … #define SPINOR_OP_RDID … #define SPINOR_OP_RDSFDP … #define SPINOR_OP_RDCR … #define SPINOR_OP_SRSTEN … #define SPINOR_OP_SRST … #define SPINOR_OP_GBULK … /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ #define SPINOR_OP_READ_4B … #define SPINOR_OP_READ_FAST_4B … #define SPINOR_OP_READ_1_1_2_4B … #define SPINOR_OP_READ_1_2_2_4B … #define SPINOR_OP_READ_1_1_4_4B … #define SPINOR_OP_READ_1_4_4_4B … #define SPINOR_OP_READ_1_1_8_4B … #define SPINOR_OP_READ_1_8_8_4B … #define SPINOR_OP_PP_4B … #define SPINOR_OP_PP_1_1_4_4B … #define SPINOR_OP_PP_1_4_4_4B … #define SPINOR_OP_PP_1_1_8_4B … #define SPINOR_OP_PP_1_8_8_4B … #define SPINOR_OP_BE_4K_4B … #define SPINOR_OP_BE_32K_4B … #define SPINOR_OP_SE_4B … /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */ #define SPINOR_OP_READ_1_1_1_DTR … #define SPINOR_OP_READ_1_2_2_DTR … #define SPINOR_OP_READ_1_4_4_DTR … #define SPINOR_OP_READ_1_1_1_DTR_4B … #define SPINOR_OP_READ_1_2_2_DTR_4B … #define SPINOR_OP_READ_1_4_4_DTR_4B … /* Used for SST flashes only. */ #define SPINOR_OP_BP … #define SPINOR_OP_AAI_WP … /* Used for Macronix and Winbond flashes. */ #define SPINOR_OP_EN4B … #define SPINOR_OP_EX4B … /* Used for Spansion flashes only. */ #define SPINOR_OP_BRWR … /* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR … #define SPINOR_OP_WD_EVCR … /* Used for GigaDevices and Winbond flashes. */ #define SPINOR_OP_ESECR … #define SPINOR_OP_PSECR … #define SPINOR_OP_RSECR … /* Status Register bits. */ #define SR_WIP … #define SR_WEL … /* meaning of other SR_* bits may differ between vendors */ #define SR_BP0 … #define SR_BP1 … #define SR_BP2 … #define SR_BP3 … #define SR_TB_BIT5 … #define SR_BP3_BIT6 … #define SR_TB_BIT6 … #define SR_SRWD … /* Spansion/Cypress specific status bits */ #define SR_E_ERR … #define SR_P_ERR … #define SR1_QUAD_EN_BIT6 … #define SR_BP_SHIFT … /* Enhanced Volatile Configuration Register bits */ #define EVCR_QUAD_EN_MICRON … /* Status Register 2 bits. */ #define SR2_QUAD_EN_BIT1 … #define SR2_LB1 … #define SR2_LB2 … #define SR2_LB3 … #define SR2_QUAD_EN_BIT7 … /* Supported SPI protocols */ #define SNOR_PROTO_INST_MASK … #define SNOR_PROTO_INST_SHIFT … #define SNOR_PROTO_INST(_nbits) … #define SNOR_PROTO_ADDR_MASK … #define SNOR_PROTO_ADDR_SHIFT … #define SNOR_PROTO_ADDR(_nbits) … #define SNOR_PROTO_DATA_MASK … #define SNOR_PROTO_DATA_SHIFT … #define SNOR_PROTO_DATA(_nbits) … #define SNOR_PROTO_IS_DTR … #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) … #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) … enum spi_nor_protocol { … }; static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto) { … } static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto) { … } static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto) { … } static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto) { … } static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto) { … } /** * struct spi_nor_hwcaps - Structure for describing the hardware capabilies * supported by the SPI controller (bus master). * @mask: the bitmask listing all the supported hw capabilies */ struct spi_nor_hwcaps { … }; /* *(Fast) Read capabilities. * MUST be ordered by priority: the higher bit position, the higher priority. * As a matter of performances, it is relevant to use Octal SPI protocols first, * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly * (Slow) Read. */ #define SNOR_HWCAPS_READ_MASK … #define SNOR_HWCAPS_READ … #define SNOR_HWCAPS_READ_FAST … #define SNOR_HWCAPS_READ_1_1_1_DTR … #define SNOR_HWCAPS_READ_DUAL … #define SNOR_HWCAPS_READ_1_1_2 … #define SNOR_HWCAPS_READ_1_2_2 … #define SNOR_HWCAPS_READ_2_2_2 … #define SNOR_HWCAPS_READ_1_2_2_DTR … #define SNOR_HWCAPS_READ_QUAD … #define SNOR_HWCAPS_READ_1_1_4 … #define SNOR_HWCAPS_READ_1_4_4 … #define SNOR_HWCAPS_READ_4_4_4 … #define SNOR_HWCAPS_READ_1_4_4_DTR … #define SNOR_HWCAPS_READ_OCTAL … #define SNOR_HWCAPS_READ_1_1_8 … #define SNOR_HWCAPS_READ_1_8_8 … #define SNOR_HWCAPS_READ_8_8_8 … #define SNOR_HWCAPS_READ_1_8_8_DTR … #define SNOR_HWCAPS_READ_8_8_8_DTR … /* * Page Program capabilities. * MUST be ordered by priority: the higher bit position, the higher priority. * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the * legacy SPI 1-1-1 protocol. * Note that Dual Page Programs are not supported because there is no existing * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory * implements such commands. */ #define SNOR_HWCAPS_PP_MASK … #define SNOR_HWCAPS_PP … #define SNOR_HWCAPS_PP_QUAD … #define SNOR_HWCAPS_PP_1_1_4 … #define SNOR_HWCAPS_PP_1_4_4 … #define SNOR_HWCAPS_PP_4_4_4 … #define SNOR_HWCAPS_PP_OCTAL … #define SNOR_HWCAPS_PP_1_1_8 … #define SNOR_HWCAPS_PP_1_8_8 … #define SNOR_HWCAPS_PP_8_8_8 … #define SNOR_HWCAPS_PP_8_8_8_DTR … #define SNOR_HWCAPS_X_X_X … #define SNOR_HWCAPS_X_X_X_DTR … #define SNOR_HWCAPS_DTR … #define SNOR_HWCAPS_ALL … /* Forward declaration that is used in 'struct spi_nor_controller_ops' */ struct spi_nor; /** * struct spi_nor_controller_ops - SPI NOR controller driver specific * operations. * @prepare: [OPTIONAL] do some preparations for the * read/write/erase/lock/unlock operations. * @unprepare: [OPTIONAL] do some post work after the * read/write/erase/lock/unlock operations. * @read_reg: read out the register. * @write_reg: write data to the register. * @read: read data from the SPI NOR. * @write: write data to the SPI NOR. * @erase: erase a sector of the SPI NOR at the offset @offs; if * not provided by the driver, SPI NOR will send the erase * opcode via write_reg(). */ struct spi_nor_controller_ops { … }; /** * enum spi_nor_cmd_ext - describes the command opcode extension in DTR mode * @SPI_NOR_EXT_NONE: no extension. This is the default, and is used in Legacy * SPI mode * @SPI_NOR_EXT_REPEAT: the extension is same as the opcode * @SPI_NOR_EXT_INVERT: the extension is the bitwise inverse of the opcode * @SPI_NOR_EXT_HEX: the extension is any hex value. The command and opcode * combine to form a 16-bit opcode. */ enum spi_nor_cmd_ext { … }; /* * Forward declarations that are used internally by the core and manufacturer * drivers. */ struct flash_info; struct spi_nor_manufacturer; struct spi_nor_flash_parameter; /** * struct spi_nor - Structure for defining the SPI NOR layer * @mtd: an mtd_info structure * @lock: the lock for the read/write/erase/lock/unlock operations * @rww: Read-While-Write (RWW) sync lock * @rww.wait: wait queue for the RWW sync * @rww.ongoing_io: the bus is busy * @rww.ongoing_rd: a read is ongoing on the chip * @rww.ongoing_pe: a program/erase is ongoing on the chip * @rww.used_banks: bitmap of the banks in use * @dev: pointer to an SPI device or an SPI NOR controller device * @spimem: pointer to the SPI memory device * @bouncebuf: bounce buffer used when the buffer passed by the MTD * layer is not DMA-able * @bouncebuf_size: size of the bounce buffer * @id: The flash's ID bytes. Always contains * SPI_NOR_MAX_ID_LEN bytes. * @info: SPI NOR part JEDEC MFR ID and other info * @manufacturer: SPI NOR manufacturer * @addr_nbytes: number of address bytes * @erase_opcode: the opcode for erasing a sector * @read_opcode: the read opcode * @read_dummy: the dummy needed by the read operation * @program_opcode: the program opcode * @sst_write_second: used by the SST write operation * @flags: flag options for the current SPI NOR (SNOR_F_*) * @cmd_ext_type: the command opcode extension type for DTR mode. * @read_proto: the SPI protocol for read operations * @write_proto: the SPI protocol for write operations * @reg_proto: the SPI protocol for read_reg/write_reg/erase operations * @sfdp: the SFDP data of the flash * @debugfs_root: pointer to the debugfs directory * @controller_ops: SPI NOR controller driver specific operations. * @params: [FLASH-SPECIFIC] SPI NOR flash parameters and settings. * The structure includes legacy flash parameters and * settings that can be overwritten by the spi_nor_fixups * hooks, or dynamically when parsing the SFDP tables. * @dirmap: pointers to struct spi_mem_dirmap_desc for reads/writes. * @priv: pointer to the private data */ struct spi_nor { … }; static inline void spi_nor_set_flash_node(struct spi_nor *nor, struct device_node *np) { … } static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor) { … } /** * spi_nor_scan() - scan the SPI NOR * @nor: the spi_nor structure * @name: the chip type name * @hwcaps: the hardware capabilities supported by the controller driver * * The drivers can use this function to scan the SPI NOR. * In the scanning, it will try to get all the necessary information to * fill the mtd_info{} and the spi_nor{}. * * The chip type name can be provided through the @name parameter. * * Return: 0 for success, others for failure. */ int spi_nor_scan(struct spi_nor *nor, const char *name, const struct spi_nor_hwcaps *hwcaps); #endif
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