// SPDX-License-Identifier: GPL-2.0 /* * Driver for Atmel QSPI Controller * * Copyright (C) 2015 Atmel Corporation * Copyright (C) 2018 Cryptera A/S * * Author: Cyrille Pitchen <[email protected]> * Author: Piotr Bugalski <[email protected]> * * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale. */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/spi/spi-mem.h> /* QSPI register offsets */ #define QSPI_CR … #define QSPI_MR … #define QSPI_RD … #define QSPI_TD … #define QSPI_SR … #define QSPI_IER … #define QSPI_IDR … #define QSPI_IMR … #define QSPI_SCR … #define QSPI_IAR … #define QSPI_ICR … #define QSPI_WICR … #define QSPI_IFR … #define QSPI_RICR … #define QSPI_SMR … #define QSPI_SKR … #define QSPI_WPMR … #define QSPI_WPSR … #define QSPI_VERSION … /* Bitfields in QSPI_CR (Control Register) */ #define QSPI_CR_QSPIEN … #define QSPI_CR_QSPIDIS … #define QSPI_CR_SWRST … #define QSPI_CR_LASTXFER … /* Bitfields in QSPI_MR (Mode Register) */ #define QSPI_MR_SMM … #define QSPI_MR_LLB … #define QSPI_MR_WDRBT … #define QSPI_MR_SMRM … #define QSPI_MR_CSMODE_MASK … #define QSPI_MR_CSMODE_NOT_RELOADED … #define QSPI_MR_CSMODE_LASTXFER … #define QSPI_MR_CSMODE_SYSTEMATICALLY … #define QSPI_MR_NBBITS_MASK … #define QSPI_MR_NBBITS(n) … #define QSPI_MR_DLYBCT_MASK … #define QSPI_MR_DLYBCT(n) … #define QSPI_MR_DLYCS_MASK … #define QSPI_MR_DLYCS(n) … /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */ #define QSPI_SR_RDRF … #define QSPI_SR_TDRE … #define QSPI_SR_TXEMPTY … #define QSPI_SR_OVRES … #define QSPI_SR_CSR … #define QSPI_SR_CSS … #define QSPI_SR_INSTRE … #define QSPI_SR_QSPIENS … #define QSPI_SR_CMD_COMPLETED … /* Bitfields in QSPI_SCR (Serial Clock Register) */ #define QSPI_SCR_CPOL … #define QSPI_SCR_CPHA … #define QSPI_SCR_SCBR_MASK … #define QSPI_SCR_SCBR(n) … #define QSPI_SCR_DLYBS_MASK … #define QSPI_SCR_DLYBS(n) … /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */ #define QSPI_ICR_INST_MASK … #define QSPI_ICR_INST(inst) … #define QSPI_ICR_OPT_MASK … #define QSPI_ICR_OPT(opt) … /* Bitfields in QSPI_IFR (Instruction Frame Register) */ #define QSPI_IFR_WIDTH_MASK … #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI … #define QSPI_IFR_WIDTH_DUAL_OUTPUT … #define QSPI_IFR_WIDTH_QUAD_OUTPUT … #define QSPI_IFR_WIDTH_DUAL_IO … #define QSPI_IFR_WIDTH_QUAD_IO … #define QSPI_IFR_WIDTH_DUAL_CMD … #define QSPI_IFR_WIDTH_QUAD_CMD … #define QSPI_IFR_INSTEN … #define QSPI_IFR_ADDREN … #define QSPI_IFR_OPTEN … #define QSPI_IFR_DATAEN … #define QSPI_IFR_OPTL_MASK … #define QSPI_IFR_OPTL_1BIT … #define QSPI_IFR_OPTL_2BIT … #define QSPI_IFR_OPTL_4BIT … #define QSPI_IFR_OPTL_8BIT … #define QSPI_IFR_ADDRL … #define QSPI_IFR_TFRTYP_MEM … #define QSPI_IFR_SAMA5D2_WRITE_TRSFR … #define QSPI_IFR_CRM … #define QSPI_IFR_NBDUM_MASK … #define QSPI_IFR_NBDUM(n) … #define QSPI_IFR_APBTFRTYP_READ … /* Bitfields in QSPI_SMR (Scrambling Mode Register) */ #define QSPI_SMR_SCREN … #define QSPI_SMR_RVDIS … /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */ #define QSPI_WPMR_WPEN … #define QSPI_WPMR_WPKEY_MASK … #define QSPI_WPMR_WPKEY(wpkey) … /* Bitfields in QSPI_WPSR (Write Protection Status Register) */ #define QSPI_WPSR_WPVS … #define QSPI_WPSR_WPVSRC_MASK … #define QSPI_WPSR_WPVSRC(src) … struct atmel_qspi_caps { … }; struct atmel_qspi { … }; struct atmel_qspi_mode { … }; static const struct atmel_qspi_mode atmel_qspi_modes[] = …; #ifdef VERBOSE_DEBUG static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz) { switch (offset) { case QSPI_CR: return "CR"; case QSPI_MR: return "MR"; case QSPI_RD: return "MR"; case QSPI_TD: return "TD"; case QSPI_SR: return "SR"; case QSPI_IER: return "IER"; case QSPI_IDR: return "IDR"; case QSPI_IMR: return "IMR"; case QSPI_SCR: return "SCR"; case QSPI_IAR: return "IAR"; case QSPI_ICR: return "ICR/WICR"; case QSPI_IFR: return "IFR"; case QSPI_RICR: return "RICR"; case QSPI_SMR: return "SMR"; case QSPI_SKR: return "SKR"; case QSPI_WPMR: return "WPMR"; case QSPI_WPSR: return "WPSR"; case QSPI_VERSION: return "VERSION"; default: snprintf(tmp, sz, "0x%02x", offset); break; } return tmp; } #endif /* VERBOSE_DEBUG */ static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset) { … } static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset) { … } static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op, const struct atmel_qspi_mode *mode) { … } static int atmel_qspi_find_mode(const struct spi_mem_op *op) { … } static bool atmel_qspi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static int atmel_qspi_set_cfg(struct atmel_qspi *aq, const struct spi_mem_op *op, u32 *offset) { … } static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static const char *atmel_qspi_get_name(struct spi_mem *spimem) { … } static const struct spi_controller_mem_ops atmel_qspi_mem_ops = …; static int atmel_qspi_setup(struct spi_device *spi) { … } static int atmel_qspi_set_cs_timing(struct spi_device *spi) { … } static void atmel_qspi_init(struct atmel_qspi *aq) { … } static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id) { … } static int atmel_qspi_probe(struct platform_device *pdev) { … } static void atmel_qspi_remove(struct platform_device *pdev) { … } static int __maybe_unused atmel_qspi_suspend(struct device *dev) { … } static int __maybe_unused atmel_qspi_resume(struct device *dev) { … } static int __maybe_unused atmel_qspi_runtime_suspend(struct device *dev) { … } static int __maybe_unused atmel_qspi_runtime_resume(struct device *dev) { … } static const struct dev_pm_ops __maybe_unused atmel_qspi_pm_ops = …; static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = …; static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = …; static const struct of_device_id atmel_qspi_dt_ids[] = …; MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids); static struct platform_driver atmel_qspi_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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