// SPDX-License-Identifier: GPL-2.0-or-later /* * ASPEED FMC/SPI Memory Controller Driver * * Copyright (c) 2015-2022, IBM Corporation. * Copyright (c) 2020, ASPEED Corporation. */ #include <linux/clk.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/spi/spi.h> #include <linux/spi/spi-mem.h> #define DEVICE_NAME … /* Type setting Register */ #define CONFIG_REG … #define CONFIG_TYPE_SPI … /* CE Control Register */ #define CE_CTRL_REG … /* CEx Control Register */ #define CE0_CTRL_REG … #define CTRL_IO_MODE_MASK … #define CTRL_IO_SINGLE_DATA … #define CTRL_IO_DUAL_DATA … #define CTRL_IO_QUAD_DATA … #define CTRL_COMMAND_SHIFT … #define CTRL_IO_ADDRESS_4B … #define CTRL_IO_DUMMY_SET(dummy) … #define CTRL_FREQ_SEL_SHIFT … #define CTRL_FREQ_SEL_MASK … #define CTRL_CE_STOP_ACTIVE … #define CTRL_IO_MODE_CMD_MASK … #define CTRL_IO_MODE_NORMAL … #define CTRL_IO_MODE_READ … #define CTRL_IO_MODE_WRITE … #define CTRL_IO_MODE_USER … #define CTRL_IO_CMD_MASK … /* CEx Address Decoding Range Register */ #define CE0_SEGMENT_ADDR_REG … /* CEx Read timing compensation register */ #define CE0_TIMING_COMPENSATION_REG … enum aspeed_spi_ctl_reg_value { … }; struct aspeed_spi; struct aspeed_spi_chip { … }; struct aspeed_spi_data { … }; #define ASPEED_SPI_MAX_NUM_CS … struct aspeed_spi { … }; static u32 aspeed_spi_get_io_mode(const struct spi_mem_op *op) { … } static void aspeed_spi_set_io_mode(struct aspeed_spi_chip *chip, u32 io_mode) { … } static void aspeed_spi_start_user(struct aspeed_spi_chip *chip) { … } static void aspeed_spi_stop_user(struct aspeed_spi_chip *chip) { … } static int aspeed_spi_read_from_ahb(void *buf, void __iomem *src, size_t len) { … } static int aspeed_spi_write_to_ahb(void __iomem *dst, const void *buf, size_t len) { … } static int aspeed_spi_send_cmd_addr(struct aspeed_spi_chip *chip, u8 addr_nbytes, u64 offset, u32 opcode) { … } static int aspeed_spi_read_reg(struct aspeed_spi_chip *chip, const struct spi_mem_op *op) { … } static int aspeed_spi_write_reg(struct aspeed_spi_chip *chip, const struct spi_mem_op *op) { … } static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip, const struct spi_mem_op *op, u64 offset, size_t len, void *buf) { … } static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip, const struct spi_mem_op *op) { … } /* support for 1-1-1, 1-1-2 or 1-1-4 */ static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static const struct aspeed_spi_data ast2400_spi_data; static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static int aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static const char *aspeed_spi_get_name(struct spi_mem *mem) { … } struct aspeed_spi_window { … }; static void aspeed_spi_get_windows(struct aspeed_spi *aspi, struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS]) { … } /* * On the AST2600, some CE windows are closed by default at reset but * U-Boot should open all. */ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip) { … } static int aspeed_spi_set_window(struct aspeed_spi *aspi, const struct aspeed_spi_window *win) { … } /* * Yet to be done when possible : * - Align mappings on flash size (we don't have the info) * - ioremap each window, not strictly necessary since the overall window * is correct. */ static const struct aspeed_spi_data ast2500_spi_data; static const struct aspeed_spi_data ast2600_spi_data; static const struct aspeed_spi_data ast2600_fmc_data; static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip, u32 local_offset, u32 size) { … } static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip); static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) { … } static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, u64 offset, size_t len, void *buf) { … } static const struct spi_controller_mem_ops aspeed_spi_mem_ops = …; static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type) { … } static void aspeed_spi_chip_enable(struct aspeed_spi *aspi, unsigned int cs, bool enable) { … } static int aspeed_spi_setup(struct spi_device *spi) { … } static void aspeed_spi_cleanup(struct spi_device *spi) { … } static void aspeed_spi_enable(struct aspeed_spi *aspi, bool enable) { … } static int aspeed_spi_probe(struct platform_device *pdev) { … } static void aspeed_spi_remove(struct platform_device *pdev) { … } /* * AHB mappings */ /* * The Segment Registers of the AST2400 and AST2500 use a 8MB unit. * The address range is encoded with absolute addresses in the overall * mapping window. */ static u32 aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg) { … } static u32 aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg) { … } static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, u32 start, u32 end) { … } /* * The Segment Registers of the AST2600 use a 1MB unit. The address * range is encoded with offsets in the overall mapping window. */ #define AST2600_SEG_ADDR_MASK … static u32 aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi, u32 reg) { … } static u32 aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi, u32 reg) { … } static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi, u32 start, u32 end) { … } /* * Read timing compensation sequences */ #define CALIBRATE_BUF_SIZE … static bool aspeed_spi_check_reads(struct aspeed_spi_chip *chip, const u8 *golden_buf, u8 *test_buf) { … } #define FREAD_TPASS(i) … /* * The timing register is shared by all devices. Only update for CE0. */ static int aspeed_spi_calibrate(struct aspeed_spi_chip *chip, u32 hdiv, const u8 *golden_buf, u8 *test_buf) { … } static bool aspeed_spi_check_calib_data(const u8 *test_buf, u32 size) { … } static const u32 aspeed_spi_hclk_divs[] = …; #define ASPEED_SPI_HCLK_DIV(i) … static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip) { … } #define TIMING_DELAY_DI … #define TIMING_DELAY_HCYCLE_MAX … #define TIMING_REG_AST2600(chip) … static int aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip *chip, u32 hdiv, const u8 *golden_buf, u8 *test_buf) { … } /* * Platform definitions */ static const struct aspeed_spi_data ast2400_fmc_data = …; static const struct aspeed_spi_data ast2400_spi_data = …; static const struct aspeed_spi_data ast2500_fmc_data = …; static const struct aspeed_spi_data ast2500_spi_data = …; static const struct aspeed_spi_data ast2600_fmc_data = …; static const struct aspeed_spi_data ast2600_spi_data = …; static const struct of_device_id aspeed_spi_matches[] = …; MODULE_DEVICE_TABLE(of, aspeed_spi_matches); static struct platform_driver aspeed_spi_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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