// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for Broadcom BCM2835 SPI Controllers * * Copyright (C) 2012 Chris Boot * Copyright (C) 2013 Stephen Warren * Copyright (C) 2015 Martin Sperl * * This driver is inspired by: * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <[email protected]> * spi-atmel.c, Copyright (C) 2006 Atmel Corporation */ #include <linux/cleanup.h> #include <linux/clk.h> #include <linux/completion.h> #include <linux/debugfs.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/dmaengine.h> #include <linux/err.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/platform_device.h> #include <linux/gpio/consumer.h> #include <linux/gpio/machine.h> /* FIXME: using GPIO lookup tables */ #include <linux/of_irq.h> #include <linux/overflow.h> #include <linux/slab.h> #include <linux/spi/spi.h> /* SPI register offsets */ #define BCM2835_SPI_CS … #define BCM2835_SPI_FIFO … #define BCM2835_SPI_CLK … #define BCM2835_SPI_DLEN … #define BCM2835_SPI_LTOH … #define BCM2835_SPI_DC … /* Bitfields in CS */ #define BCM2835_SPI_CS_LEN_LONG … #define BCM2835_SPI_CS_DMA_LEN … #define BCM2835_SPI_CS_CSPOL2 … #define BCM2835_SPI_CS_CSPOL1 … #define BCM2835_SPI_CS_CSPOL0 … #define BCM2835_SPI_CS_RXF … #define BCM2835_SPI_CS_RXR … #define BCM2835_SPI_CS_TXD … #define BCM2835_SPI_CS_RXD … #define BCM2835_SPI_CS_DONE … #define BCM2835_SPI_CS_LEN … #define BCM2835_SPI_CS_REN … #define BCM2835_SPI_CS_ADCS … #define BCM2835_SPI_CS_INTR … #define BCM2835_SPI_CS_INTD … #define BCM2835_SPI_CS_DMAEN … #define BCM2835_SPI_CS_TA … #define BCM2835_SPI_CS_CSPOL … #define BCM2835_SPI_CS_CLEAR_RX … #define BCM2835_SPI_CS_CLEAR_TX … #define BCM2835_SPI_CS_CPOL … #define BCM2835_SPI_CS_CPHA … #define BCM2835_SPI_CS_CS_10 … #define BCM2835_SPI_CS_CS_01 … #define BCM2835_SPI_FIFO_SIZE … #define BCM2835_SPI_FIFO_SIZE_3_4 … #define BCM2835_SPI_DMA_MIN_LENGTH … #define BCM2835_SPI_MODE_BITS … #define DRV_NAME … /* define polling limits */ static unsigned int polling_limit_us = …; module_param(polling_limit_us, uint, 0664); MODULE_PARM_DESC(…) …; /** * struct bcm2835_spi - BCM2835 SPI controller * @regs: base address of register map * @clk: core clock, divided to calculate serial clock * @cs_gpio: chip-select GPIO descriptor * @clk_hz: core clock cached speed * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full * @tfr: SPI transfer currently processed * @ctlr: SPI controller reverse lookup * @tx_buf: pointer whence next transmitted byte is read * @rx_buf: pointer where next received byte is written * @tx_len: remaining bytes to transmit * @rx_len: remaining bytes to receive * @tx_prologue: bytes transmitted without DMA if first TX sglist entry's * length is not a multiple of 4 (to overcome hardware limitation) * @rx_prologue: bytes received without DMA if first RX sglist entry's * length is not a multiple of 4 (to overcome hardware limitation) * @tx_spillover: whether @tx_prologue spills over to second TX sglist entry * @debugfs_dir: the debugfs directory - neede to remove debugfs when * unloading the module * @count_transfer_polling: count of how often polling mode is used * @count_transfer_irq: count of how often interrupt mode is used * @count_transfer_irq_after_polling: count of how often we fall back to * interrupt mode after starting in polling mode. * These are counted as well in @count_transfer_polling and * @count_transfer_irq * @count_transfer_dma: count how often dma mode is used * @target: SPI target currently selected * (used by bcm2835_spi_dma_tx_done() to write @clear_rx_cs) * @tx_dma_active: whether a TX DMA descriptor is in progress * @rx_dma_active: whether a RX DMA descriptor is in progress * (used by bcm2835_spi_dma_tx_done() to handle a race) * @fill_tx_desc: preallocated TX DMA descriptor used for RX-only transfers * (cyclically copies from zero page to TX FIFO) * @fill_tx_addr: bus address of zero page */ struct bcm2835_spi { … }; /** * struct bcm2835_spidev - BCM2835 SPI target * @prepare_cs: precalculated CS register value for ->prepare_message() * (uses target-specific clock polarity and phase settings) * @clear_rx_desc: preallocated RX DMA descriptor used for TX-only transfers * (cyclically clears RX FIFO by writing @clear_rx_cs to CS register) * @clear_rx_addr: bus address of @clear_rx_cs * @clear_rx_cs: precalculated CS register value to clear RX FIFO * (uses target-specific clock polarity and phase settings) */ struct bcm2835_spidev { … }; #if defined(CONFIG_DEBUG_FS) static void bcm2835_debugfs_create(struct bcm2835_spi *bs, const char *dname) { … } static void bcm2835_debugfs_remove(struct bcm2835_spi *bs) { … } #else static void bcm2835_debugfs_create(struct bcm2835_spi *bs, const char *dname) { } static void bcm2835_debugfs_remove(struct bcm2835_spi *bs) { } #endif /* CONFIG_DEBUG_FS */ static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned int reg) { … } static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned int reg, u32 val) { … } static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs) { … } static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs) { … } /** * bcm2835_rd_fifo_count() - blindly read exactly @count bytes from RX FIFO * @bs: BCM2835 SPI controller * @count: bytes to read from RX FIFO * * The caller must ensure that @bs->rx_len is greater than or equal to @count, * that the RX FIFO contains at least @count bytes and that the DMA Enable flag * in the CS register is set (such that a read from the FIFO register receives * 32-bit instead of just 8-bit). Moreover @bs->rx_buf must not be %NULL. */ static inline void bcm2835_rd_fifo_count(struct bcm2835_spi *bs, int count) { … } /** * bcm2835_wr_fifo_count() - blindly write exactly @count bytes to TX FIFO * @bs: BCM2835 SPI controller * @count: bytes to write to TX FIFO * * The caller must ensure that @bs->tx_len is greater than or equal to @count, * that the TX FIFO can accommodate @count bytes and that the DMA Enable flag * in the CS register is set (such that a write to the FIFO register transmits * 32-bit instead of just 8-bit). */ static inline void bcm2835_wr_fifo_count(struct bcm2835_spi *bs, int count) { … } /** * bcm2835_wait_tx_fifo_empty() - busy-wait for TX FIFO to empty * @bs: BCM2835 SPI controller * * The caller must ensure that the RX FIFO can accommodate as many bytes * as have been written to the TX FIFO: Transmission is halted once the * RX FIFO is full, causing this function to spin forever. */ static inline void bcm2835_wait_tx_fifo_empty(struct bcm2835_spi *bs) { … } /** * bcm2835_rd_fifo_blind() - blindly read up to @count bytes from RX FIFO * @bs: BCM2835 SPI controller * @count: bytes available for reading in RX FIFO */ static inline void bcm2835_rd_fifo_blind(struct bcm2835_spi *bs, int count) { … } /** * bcm2835_wr_fifo_blind() - blindly write up to @count bytes to TX FIFO * @bs: BCM2835 SPI controller * @count: bytes available for writing in TX FIFO */ static inline void bcm2835_wr_fifo_blind(struct bcm2835_spi *bs, int count) { … } static void bcm2835_spi_reset_hw(struct bcm2835_spi *bs) { … } static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id) { … } static int bcm2835_spi_transfer_one_irq(struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *tfr, u32 cs, bool fifo_empty) { … } /** * bcm2835_spi_transfer_prologue() - transfer first few bytes without DMA * @ctlr: SPI host controller * @tfr: SPI transfer * @bs: BCM2835 SPI controller * @cs: CS register * * A limitation in DMA mode is that the FIFO must be accessed in 4 byte chunks. * Only the final write access is permitted to transmit less than 4 bytes, the * SPI controller deduces its intended size from the DLEN register. * * If a TX or RX sglist contains multiple entries, one per page, and the first * entry starts in the middle of a page, that first entry's length may not be * a multiple of 4. Subsequent entries are fine because they span an entire * page, hence do have a length that's a multiple of 4. * * This cannot happen with kmalloc'ed buffers (which is what most clients use) * because they are contiguous in physical memory and therefore not split on * page boundaries by spi_map_buf(). But it *can* happen with vmalloc'ed * buffers. * * The DMA engine is incapable of combining sglist entries into a continuous * stream of 4 byte chunks, it treats every entry separately: A TX entry is * rounded up a to a multiple of 4 bytes by transmitting surplus bytes, an RX * entry is rounded up by throwing away received bytes. * * Overcome this limitation by transferring the first few bytes without DMA: * E.g. if the first TX sglist entry's length is 23 and the first RX's is 42, * write 3 bytes to the TX FIFO but read only 2 bytes from the RX FIFO. * The residue of 1 byte in the RX FIFO is picked up by DMA. Together with * the rest of the first RX sglist entry it makes up a multiple of 4 bytes. * * Should the RX prologue be larger, say, 3 vis-à-vis a TX prologue of 1, * write 1 + 4 = 5 bytes to the TX FIFO and read 3 bytes from the RX FIFO. * Caution, the additional 4 bytes spill over to the second TX sglist entry * if the length of the first is *exactly* 1. * * At most 6 bytes are written and at most 3 bytes read. Do we know the * transfer has this many bytes? Yes, see BCM2835_SPI_DMA_MIN_LENGTH. * * The FIFO is normally accessed with 8-bit width by the CPU and 32-bit width * by the DMA engine. Toggling the DMA Enable flag in the CS register switches * the width but also garbles the FIFO's contents. The prologue must therefore * be transmitted in 32-bit width to ensure that the following DMA transfer can * pick up the residue in the RX FIFO in ungarbled form. */ static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr, struct spi_transfer *tfr, struct bcm2835_spi *bs, u32 cs) { … } /** * bcm2835_spi_undo_prologue() - reconstruct original sglist state * @bs: BCM2835 SPI controller * * Undo changes which were made to an SPI transfer's sglist when transmitting * the prologue. This is necessary to ensure the same memory ranges are * unmapped that were originally mapped. */ static void bcm2835_spi_undo_prologue(struct bcm2835_spi *bs) { … } /** * bcm2835_spi_dma_rx_done() - callback for DMA RX channel * @data: SPI host controller * * Used for bidirectional and RX-only transfers. */ static void bcm2835_spi_dma_rx_done(void *data) { … } /** * bcm2835_spi_dma_tx_done() - callback for DMA TX channel * @data: SPI host controller * * Used for TX-only transfers. */ static void bcm2835_spi_dma_tx_done(void *data) { … } /** * bcm2835_spi_prepare_sg() - prepare and submit DMA descriptor for sglist * @ctlr: SPI host controller * @tfr: SPI transfer * @bs: BCM2835 SPI controller * @target: BCM2835 SPI target * @is_tx: whether to submit DMA descriptor for TX or RX sglist * * Prepare and submit a DMA descriptor for the TX or RX sglist of @tfr. * Return 0 on success or a negative error number. */ static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr, struct spi_transfer *tfr, struct bcm2835_spi *bs, struct bcm2835_spidev *target, bool is_tx) { … } /** * bcm2835_spi_transfer_one_dma() - perform SPI transfer using DMA engine * @ctlr: SPI host controller * @tfr: SPI transfer * @target: BCM2835 SPI target * @cs: CS register * * For *bidirectional* transfers (both tx_buf and rx_buf are non-%NULL), set up * the TX and RX DMA channel to copy between memory and FIFO register. * * For *TX-only* transfers (rx_buf is %NULL), copying the RX FIFO's contents to * memory is pointless. However not reading the RX FIFO isn't an option either * because transmission is halted once it's full. As a workaround, cyclically * clear the RX FIFO by setting the CLEAR_RX bit in the CS register. * * The CS register value is precalculated in bcm2835_spi_setup(). Normally * this is called only once, on target registration. A DMA descriptor to write * this value is preallocated in bcm2835_dma_init(). All that's left to do * when performing a TX-only transfer is to submit this descriptor to the RX * DMA channel. Latency is thereby minimized. The descriptor does not * generate any interrupts while running. It must be terminated once the * TX DMA channel is done. * * Clearing the RX FIFO is paced by the DREQ signal. The signal is asserted * when the RX FIFO becomes half full, i.e. 32 bytes. (Tuneable with the DC * register.) Reading 32 bytes from the RX FIFO would normally require 8 bus * accesses, whereas clearing it requires only 1 bus access. So an 8-fold * reduction in bus traffic and thus energy consumption is achieved. * * For *RX-only* transfers (tx_buf is %NULL), fill the TX FIFO by cyclically * copying from the zero page. The DMA descriptor to do this is preallocated * in bcm2835_dma_init(). It must be terminated once the RX DMA channel is * done and can then be reused. * * The BCM2835 DMA driver autodetects when a transaction copies from the zero * page and utilizes the DMA controller's ability to synthesize zeroes instead * of copying them from memory. This reduces traffic on the memory bus. The * feature is not available on so-called "lite" channels, but normally TX DMA * is backed by a full-featured channel. * * Zero-filling the TX FIFO is paced by the DREQ signal. Unfortunately the * BCM2835 SPI controller continues to assert DREQ even after the DLEN register * has been counted down to zero (hardware erratum). Thus, when the transfer * has finished, the DMA engine zero-fills the TX FIFO until it is half full. * (Tuneable with the DC register.) So up to 9 gratuitous bus accesses are * performed at the end of an RX-only transfer. */ static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr, struct spi_transfer *tfr, struct bcm2835_spidev *target, u32 cs) { … } static bool bcm2835_spi_can_dma(struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *tfr) { … } static void bcm2835_dma_release(struct spi_controller *ctlr, struct bcm2835_spi *bs) { … } static int bcm2835_dma_init(struct spi_controller *ctlr, struct device *dev, struct bcm2835_spi *bs) { … } static int bcm2835_spi_transfer_one_poll(struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *tfr, u32 cs) { … } static int bcm2835_spi_transfer_one(struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *tfr) { … } static int bcm2835_spi_prepare_message(struct spi_controller *ctlr, struct spi_message *msg) { … } static void bcm2835_spi_handle_err(struct spi_controller *ctlr, struct spi_message *msg) { … } static void bcm2835_spi_cleanup(struct spi_device *spi) { … } static int bcm2835_spi_setup_dma(struct spi_controller *ctlr, struct spi_device *spi, struct bcm2835_spi *bs, struct bcm2835_spidev *target) { … } static size_t bcm2835_spi_max_transfer_size(struct spi_device *spi) { … } static int bcm2835_spi_setup(struct spi_device *spi) { … } static int bcm2835_spi_probe(struct platform_device *pdev) { … } static void bcm2835_spi_remove(struct platform_device *pdev) { … } static const struct of_device_id bcm2835_spi_match[] = …; MODULE_DEVICE_TABLE(of, bcm2835_spi_match); static struct platform_driver bcm2835_spi_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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