// SPDX-License-Identifier: GPL-2.0-only /* * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers * * Copyright 2016 Broadcom */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/ioport.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/spi/spi.h> #include <linux/mtd/spi-nor.h> #include <linux/sysfs.h> #include <linux/types.h> #include "spi-bcm-qspi.h" #define DRIVER_NAME … /* BSPI register offsets */ #define BSPI_REVISION_ID … #define BSPI_SCRATCH … #define BSPI_MAST_N_BOOT_CTRL … #define BSPI_BUSY_STATUS … #define BSPI_INTR_STATUS … #define BSPI_B0_STATUS … #define BSPI_B0_CTRL … #define BSPI_B1_STATUS … #define BSPI_B1_CTRL … #define BSPI_STRAP_OVERRIDE_CTRL … #define BSPI_FLEX_MODE_ENABLE … #define BSPI_BITS_PER_CYCLE … #define BSPI_BITS_PER_PHASE … #define BSPI_CMD_AND_MODE_BYTE … #define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE … #define BSPI_BSPI_XOR_VALUE … #define BSPI_BSPI_XOR_ENABLE … #define BSPI_BSPI_PIO_MODE_ENABLE … #define BSPI_BSPI_PIO_IODIR … #define BSPI_BSPI_PIO_DATA … /* RAF register offsets */ #define BSPI_RAF_START_ADDR … #define BSPI_RAF_NUM_WORDS … #define BSPI_RAF_CTRL … #define BSPI_RAF_FULLNESS … #define BSPI_RAF_WATERMARK … #define BSPI_RAF_STATUS … #define BSPI_RAF_READ_DATA … #define BSPI_RAF_WORD_CNT … #define BSPI_RAF_CURR_ADDR … /* Override mode masks */ #define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE … #define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL … #define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE … #define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD … #define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE … #define BSPI_ADDRLEN_3BYTES … #define BSPI_ADDRLEN_4BYTES … #define BSPI_RAF_STATUS_FIFO_EMPTY_MASK … #define BSPI_RAF_CTRL_START_MASK … #define BSPI_RAF_CTRL_CLEAR_MASK … #define BSPI_BPP_MODE_SELECT_MASK … #define BSPI_BPP_ADDR_SELECT_MASK … #define BSPI_READ_LENGTH … /* MSPI register offsets */ #define MSPI_SPCR0_LSB … #define MSPI_SPCR0_MSB … #define MSPI_SPCR0_MSB_CPHA … #define MSPI_SPCR0_MSB_CPOL … #define MSPI_SPCR0_MSB_BITS_SHIFT … #define MSPI_SPCR1_LSB … #define MSPI_SPCR1_MSB … #define MSPI_NEWQP … #define MSPI_ENDQP … #define MSPI_SPCR2 … #define MSPI_MSPI_STATUS … #define MSPI_CPTQP … #define MSPI_SPCR3 … #define MSPI_REV … #define MSPI_TXRAM … #define MSPI_RXRAM … #define MSPI_CDRAM … #define MSPI_WRITE_LOCK … #define MSPI_MASTER_BIT … #define MSPI_NUM_CDRAM … #define MSPI_CDRAM_OUTP … #define MSPI_CDRAM_CONT_BIT … #define MSPI_CDRAM_BITSE_BIT … #define MSPI_CDRAM_DT_BIT … #define MSPI_CDRAM_PCS … #define MSPI_SPCR2_SPE … #define MSPI_SPCR2_CONT_AFTER_CMD … #define MSPI_SPCR3_FASTBR … #define MSPI_SPCR3_FASTDT … #define MSPI_SPCR3_SYSCLKSEL_MASK … #define MSPI_SPCR3_SYSCLKSEL_27 … #define MSPI_SPCR3_SYSCLKSEL_108 … #define MSPI_SPCR3_TXRXDAM_MASK … #define MSPI_SPCR3_DAM_8BYTE … #define MSPI_SPCR3_DAM_16BYTE … #define MSPI_SPCR3_DAM_32BYTE … #define MSPI_SPCR3_HALFDUPLEX … #define MSPI_SPCR3_HDOUTTYPE … #define MSPI_SPCR3_DATA_REG_SZ … #define MSPI_SPCR3_CPHARX … #define MSPI_MSPI_STATUS_SPIF … #define INTR_BASE_BIT_SHIFT … #define INTR_COUNT … #define NUM_CHIPSELECT … #define QSPI_SPBR_MAX … #define MSPI_BASE_FREQ … #define OPCODE_DIOR … #define OPCODE_QIOR … #define OPCODE_DIOR_4B … #define OPCODE_QIOR_4B … #define MAX_CMD_SIZE … #define ADDR_4MB_MASK … /* stop at end of transfer, no other reason */ #define TRANS_STATUS_BREAK_NONE … /* stop at end of spi_message */ #define TRANS_STATUS_BREAK_EOM … /* stop at end of spi_transfer if delay */ #define TRANS_STATUS_BREAK_DELAY … /* stop at end of spi_transfer if cs_change */ #define TRANS_STATUS_BREAK_CS_CHANGE … /* stop if we run out of bytes */ #define TRANS_STATUS_BREAK_NO_BYTES … /* events that make us stop filling TX slots */ #define TRANS_STATUS_BREAK_TX … /* events that make us deassert CS */ #define TRANS_STATUS_BREAK_DESELECT … /* * Used for writing and reading data in the right order * to TXRAM and RXRAM when used as 32-bit registers respectively */ #define swap4bytes(__val) … struct bcm_qspi_parms { … }; struct bcm_xfer_mode { … }; enum base_type { … }; enum irq_source { … }; struct bcm_qspi_irq { … }; struct bcm_qspi_dev_id { … }; struct qspi_trans { … }; struct bcm_qspi { … }; static inline bool has_bspi(struct bcm_qspi *qspi) { … } /* hardware supports spcr3 and fast baud-rate */ static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) { … } /* hardware supports sys clk 108Mhz */ static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi) { … } static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi) { … } static u32 bcm_qspi_calc_spbr(u32 clk_speed_hz, const struct bcm_qspi_parms *xp) { … } /* Read qspi controller register*/ static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type, unsigned int offset) { … } /* Write qspi controller register*/ static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type, unsigned int offset, unsigned int data) { … } /* BSPI helpers */ static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi) { … } static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi) { … } static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi) { … } static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi) { … } static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi) { … } static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi) { … } static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi) { … } static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi) { … } static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte, int bpp, int bpc, int flex_mode) { … } static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi, const struct spi_mem_op *op, int hp) { … } static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi, const struct spi_mem_op *op, int hp) { … } static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi, const struct spi_mem_op *op, int hp) { … } static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi) { … } static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi) { … } static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs) { … } static bool bcmspi_parms_did_change(const struct bcm_qspi_parms * const cur, const struct bcm_qspi_parms * const prev) { … } /* MSPI helpers */ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi, const struct bcm_qspi_parms *xp) { … } static void bcm_qspi_update_parms(struct bcm_qspi *qspi, struct spi_device *spi, struct spi_transfer *trans) { … } static int bcm_qspi_setup(struct spi_device *spi) { … } static bool bcm_qspi_mspi_transfer_is_last(struct bcm_qspi *qspi, struct qspi_trans *qt) { … } static int update_qspi_trans_byte_count(struct bcm_qspi *qspi, struct qspi_trans *qt, int flags) { … } static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot) { … } static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot) { … } static inline u32 read_rxram_slot_u32(struct bcm_qspi *qspi, int slot) { … } static inline u64 read_rxram_slot_u64(struct bcm_qspi *qspi, int slot) { … } static void read_from_hw(struct bcm_qspi *qspi, int slots) { … } static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot, u8 val) { … } static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot, u16 val) { … } static inline void write_txram_slot_u32(struct bcm_qspi *qspi, int slot, u32 val) { … } static inline void write_txram_slot_u64(struct bcm_qspi *qspi, int slot, u64 val) { … } static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot) { … } static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val) { … } /* Return number of slots written */ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi) { … } static int bcm_qspi_bspi_exec_mem_op(struct spi_device *spi, const struct spi_mem_op *op) { … } static int bcm_qspi_transfer_one(struct spi_controller *host, struct spi_device *spi, struct spi_transfer *trans) { … } static int bcm_qspi_mspi_exec_mem_op(struct spi_device *spi, const struct spi_mem_op *op) { … } static int bcm_qspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static void bcm_qspi_cleanup(struct spi_device *spi) { … } static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id) { … } static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id) { … } static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id) { … } static irqreturn_t bcm_qspi_l1_isr(int irq, void *dev_id) { … } static const struct bcm_qspi_irq qspi_irq_tab[] = …; static void bcm_qspi_bspi_init(struct bcm_qspi *qspi) { … } static void bcm_qspi_hw_init(struct bcm_qspi *qspi) { … } static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi) { … } static const struct spi_controller_mem_ops bcm_qspi_mem_ops = …; struct bcm_qspi_data { … }; static const struct bcm_qspi_data bcm_qspi_no_rev_data = …; static const struct bcm_qspi_data bcm_qspi_rev_data = …; static const struct bcm_qspi_data bcm_qspi_spcr3_data = …; static const struct of_device_id bcm_qspi_of_match[] __maybe_unused = …; MODULE_DEVICE_TABLE(of, bcm_qspi_of_match); int bcm_qspi_probe(struct platform_device *pdev, struct bcm_qspi_soc_intc *soc_intc) { … } /* probe function to be called by SoC specific platform driver probe */ EXPORT_SYMBOL_GPL(…); void bcm_qspi_remove(struct platform_device *pdev) { … } /* function to be called by SoC specific platform driver remove() */ EXPORT_SYMBOL_GPL(…); static int __maybe_unused bcm_qspi_suspend(struct device *dev) { struct bcm_qspi *qspi = dev_get_drvdata(dev); /* store the override strap value */ if (!bcm_qspi_bspi_ver_three(qspi)) qspi->s3_strap_override_ctrl = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); spi_controller_suspend(qspi->host); clk_disable_unprepare(qspi->clk); bcm_qspi_hw_uninit(qspi); return 0; }; static int __maybe_unused bcm_qspi_resume(struct device *dev) { … } SIMPLE_DEV_PM_OPS(bcm_qspi_pm_ops, bcm_qspi_suspend, bcm_qspi_resume); /* pm_ops to be called by SoC specific platform driver */ EXPORT_SYMBOL_GPL(…); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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